公开(公告)号：US20230376662A1

公开(公告)日：2023-11-23

申请号：US17746512

申请日：2022-05-17

Applicant: Xilinx, Inc.

Inventor： Nageshwar Reddy Peddamgari ,  Sourabh Anand ,  Vasudha Annam ,  Chandra Sekhar Mulpuri

IPC: G06F30/3308

CPC classification number: G06F30/3308

Abstract: Methods and systems for simulating RTL models in combination with behavioral models involve generating an overall simulation model from a circuit design by a simulation tool of an EDA system. The overall simulation model includes respective behavioral simulation models of components of the circuit design. A register transfer level (RTL) simulation model of a particular component of the components of the circuit design is generated by an extractor tool of the EDA system. The respective behavioral simulation model of the particular component in the overall simulation model is replaced with the RTL simulation model, and a simulation that executes the overall simulation model and the RTL simulation model in place of the behavioral simulation model of the particular component is performed.

公开(公告)号：US11983478B2

公开(公告)日：2024-05-14

申请号：US17691771

申请日：2022-03-10

Applicant: Xilinx, Inc.

Inventor： Shant Chandrakar ,  Sourabh Anand ,  Shubham Rajput ,  Kameshwar Chandrasekar

IPC: G06F30/394 ,  G06F30/31 ,  G06F30/327 ,  G06F30/392

CPC classification number: G06F30/394 ,  G06F30/31 ,  G06F30/327 ,  G06F30/392

Abstract: A machine learning-based process includes identifying a first set of features that includes features of a reference implementation of a circuit design and features of a synthesized version of a modified version of the circuit design. A first classification model is applied to the first set of features, and the first classification model indicates a full implementation flow or an incremental implementation flow. The full implementation flow is performed on the synthesized version of the modified version in response to the first classification model indicating the full implementation flow, and the incremental implementation flow is performed on the synthesized version of the modified version in response to the first classification model indicating the incremental implementation flow. The full and incremental implementation flows generate implementation data that is suitable for making an integrated circuit (IC).