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公开(公告)号:US20180039886A1
公开(公告)日:2018-02-08
申请号:US15230164
申请日:2016-08-05
Applicant: Xilinx, Inc.
Inventor: Yaman Umuroglu , Michaela Blott
CPC classification number: G06N3/08 , G06N3/04 , G06N3/063 , H03K19/17732
Abstract: In an example, a circuit of a neural network implemented in an integrated circuit (IC) includes a layer of hardware neurons, the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values, each of the hardware neurons including: a logic circuit having inputs that receive first logic signals from at least a portion of the plurality of inputs and outputs that supply second logic signals corresponding to an exclusive NOR (XNOR) of the first logic signals and at least a portion of the plurality of weights; a counter circuit having inputs that receive the second logic signals and an output that supplies a count signal indicative of the number of the second logic signals having a predefined logic state; and a compare circuit having an input that receives the count signal and an output that supplies a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values; wherein the logic signal output by the compare circuit of each of the hardware neurons is provided as a respective one of the plurality of outputs.
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公开(公告)号:US12067484B2
公开(公告)日:2024-08-20
申请号:US16449264
申请日:2019-06-21
Applicant: Xilinx, Inc.
Inventor: Yaman Umuroglu , Nicholas Fraser , Michaela Blott , Kristof Denolf , Kornelis A. Vissers
Abstract: An example method of training a neural network includes defining hardware building blocks (HBBs), neuron equivalents (NEQs), and conversion procedures from NEQs to HBBs; defining the neural network using the NEQs in a machine learning framework; training the neural network on a training platform; and converting the neural network as trained into a netlist of HBBs using the conversion procedures to convert the NEQs in the neural network to the HBBs of the netlist.
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公开(公告)号:US10089577B2
公开(公告)日:2018-10-02
申请号:US15230164
申请日:2016-08-05
Applicant: Xilinx, Inc.
Inventor: Yaman Umuroglu , Michaela Blott
Abstract: In an example, a circuit of a neural network implemented in an integrated circuit (IC) includes a layer of hardware neurons, the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values, each of the hardware neurons including: a logic circuit having inputs that receive first logic signals from at least a portion of the plurality of inputs and outputs that supply second logic signals corresponding to an exclusive NOR (XNOR) of the first logic signals and at least a portion of the plurality of weights; a counter circuit having inputs that receive the second logic signals and an output that supplies a count signal indicative of the number of the second logic signals having a predefined logic state; and a compare circuit having an input that receives the count signal and an output that supplies a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values; wherein the logic signal output by the compare circuit of each of the hardware neurons is provided as a respective one of the plurality of outputs.
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