SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES
    2.
    发明申请
    SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES 审中-公开
    具有集成串行接口的订户线接口电路

    公开(公告)号:US20100166434A1

    公开(公告)日:2010-07-01

    申请号:US12347992

    申请日:2008-12-31

    IPC分类号: H04B10/08

    CPC分类号: H04L12/2885

    摘要: Methods and apparatus for communicating include communicating frames of data at a frequency f1 serially from a first device to a second device using a first unidirectional data line. The frames have a first timeslot allocation of s timeslots. A clock signal having a frequency f2 is generated within the second device, wherein f 2 f 1 ≈ n · s , wherein n>1. The first unidirectional data line is sampled every n clock cycles of the clock signal for a plurality of the timeslots.

    摘要翻译: 用于通信的方法和装置包括使用第一单向数据线将频率f1从第一设备到第二设备串行地传送数据帧。 帧具有时隙的第一时隙分配。 在第二装置内产生具有频率f2的时钟信号,其中f 2 f 1≈n·s,其中n> 1。 在多个时隙的时钟信号的每n个时钟周期对第一单向数据线进行采样。

    SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES
    3.
    发明申请
    SUBSCRIBER LINE INTERFACE CIRCUITRY WITH INTEGRATED SERIAL INTERFACES 审中-公开
    具有集成串行接口的订户线接口电路

    公开(公告)号:US20100166019A1

    公开(公告)日:2010-07-01

    申请号:US12347987

    申请日:2008-12-31

    IPC分类号: H04J3/00

    CPC分类号: H04J3/1694 H04L7/0008

    摘要: Methods and apparatus for communicating include communicating frames of data having a first timeslot allocation of s timeslots serially from a first device to a second device using a first unidirectional data line at a frequency f1. An edge of each frame as a detected edge. A clock signal having a frequency f2 is generated in response to the detected edges, wherein f 2 f 1 ≈ n · s , wherein n>1, wherein the clock signal is maintained substantially synchronous to the detected edges. Frames of data having a second timeslot allocation of s timeslots are communicated serially from the second device to the first device using a second unidirectional data line at the frequency f1 as derived from f2.

    摘要翻译: 用于通信的方法和装置包括使用频率为f1的第一单向数据线将第一时隙的第一时隙分配的数据帧从第一设备串行地传送到第二设备。 每个帧的边缘作为检测到的边缘。 响应于检测到的边缘产生具有频率f2的时钟信号,其中f 2 f 1≈n·s,其中n> 1,其中时钟信号保持与检测到的边缘基本同步。 具有s时隙的第二时隙分配的数据帧,使用从f2导出的频率f1的第二单向数据线,从第二设备串行地传送到第一设备。