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    Automatic method and system for instantiating built-in-test (BIST) modules in ASIC memory designs
    2.
    发明授权
    Automatic method and system for instantiating built-in-test (BIST) modules in ASIC memory designs 有权
    用于在ASIC存储器设计中实例化内置测试（BIST）模块的自动方法和系统

    公开(公告)号：US07139991B2

    公开(公告)日：2006-11-21

    申请号：US11107585

    申请日：2005-04-14

    申请人： Yaron Kretchmer ,  Michael Porter ,  Thomas Obrien

    发明人： Yaron Kretchmer ,  Michael Porter ,  Thomas Obrien

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G11C29/12 ,  G11C2029/0401

    摘要： A method and system for automatically instantiating built-in-system test (BIST) modules in memory designs is disclosed. The method and system include providing a server over a network that integrates a set of design tools, including an automated front-end software process and an automated back-end software process. According to the method and system, a user may access the server over the network and enter a request for a memory design. The front-end software process is then executed to automatically generate a netlist of a BIST from the user request. Thereafter, the back-end software process is executed to automatically generate a placement and route view of the BIST.

    摘要翻译： 公开了一种在内存设计中自动实例化内置系统测试（BIST）模块的方法和系统。 该方法和系统包括通过网络提供集成一组设计工具的服务器，包括自动化前端软件过程和自动后端软件过程。 根据方法和系统，用户可以通过网络访问服务器并输入对存储器设计的请求。 然后执行前端软件过程，以根据用户请求自动生成BIST的网表。 此后，执行后端软件处理以自动生成BIST的布局和路线视图。

    Automatic method and system for instantiating built-in-test (BIST) modules in ASIC memory designs
    3.
    发明授权
    Automatic method and system for instantiating built-in-test (BIST) modules in ASIC memory designs 失效
    用于在ASIC存储器设计中实例化内置测试（BIST）模块的自动方法和系统

    公开(公告)号：US06931606B1

    公开(公告)日：2005-08-16

    申请号：US09978141

    申请日：2001-10-15

    申请人： Yaron Kretchmer ,  Michael Porter ,  Thomas OBrien

    发明人： Yaron Kretchmer ,  Michael Porter ,  Thomas OBrien

    IPC分类号： G01R31/28 ,  G06F9/45 ,  G06F17/50 ,  G11C29/12

    CPC分类号： G11C29/12 ,  G11C2029/0401

    摘要： A method and system for automatically instantiating built-in-system test (BIST) modules in memory designs is disclosed. The method and system include providing a server over a network that integrates a set of design tools, including an automated front-end software process and an automated back-end software process. According to the method and system, a user may access the server over the network and enter a request for a memory design. The front-end software process is then executed to automatically generate a netlist of a BIST from the user request. Thereafter, the back-end software process is executed to automatically generate a placement and route view of the BIST.

    摘要翻译： 公开了一种在内存设计中自动实例化内置系统测试（BIST）模块的方法和系统。 该方法和系统包括通过网络提供集成一组设计工具的服务器，包括自动化前端软件过程和自动后端软件过程。 根据该方法和系统，用户可以通过网络访问服务器并输入对存储器设计的请求。 然后执行前端软件过程，以根据用户请求自动生成BIST的网表。 此后，执行后端软件处理以自动生成BIST的布局和路线视图。

    Reduced power distribution mesh resistance using a modified swiss-cheese slotting pattern
    4.
    发明授权
    Reduced power distribution mesh resistance using a modified swiss-cheese slotting pattern 有权
    使用改良的瑞士干酪开槽模式降低配电网阻力

    公开(公告)号：US07365413B1

    公开(公告)日：2008-04-29

    申请号：US10940511

    申请日：2004-09-13

    申请人： Yaron Kretchmer ,  Fredrik Haghverdian

    发明人： Yaron Kretchmer ,  Fredrik Haghverdian

    IPC分类号： H01L29/06

    CPC分类号： H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electrical interconnects with a slotting pattern are provided in the present invention. In addition, the masks for making such interconnects and semiconductor devices incorporating such interconnects are also provided in the present invention. The slotting pattern may be designed to minimize dishing effects of the interconnects as a result of planarization. Further, the slotting pattern may be designed to minimize resistance in the interconnects. For instance, the slotting pattern may include slots that are staggered, evenly aligned, or a combination of both staggered and evenly aligned. In addition, the slots may be spaced apart such that electrical paths are shorter across the interconnects. By incorporating such interconnects in semiconductor devices, better performing semiconductor devices can be realized.

    摘要翻译： 在本发明中提供具有开槽图案的电互连。 此外，在本发明中还提供了用于制造这种互连的掩模和并入这种互连的半导体器件。 开槽图案可以被设计成最小化作为平坦化的结果的互连的凹陷效应。 此外，开槽图案可以被设计成使互连中的电阻最小化。 例如，开槽图案可以包括交错，均匀排列的或者交错的和均匀排列的组合的槽。 此外，槽可以间隔开，使得电气路径在互连件之间较短。 通过将这种互连结合在半导体器件中，可以实现更好的半导体器件。

    Power-driven timing analysis and placement for programmable logic
    5.
    发明授权
    Power-driven timing analysis and placement for programmable logic 有权
    用于可编程逻辑的功率驱动时序分析和放置

    公开(公告)号：US07861190B1

    公开(公告)日：2010-12-28

    申请号：US10907049

    申请日：2005-03-17

    申请人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    发明人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  Y02T10/82

    摘要： An integrated circuit is divided into two or more different regions, each region being a different voltage domain. In each of the regions, a voltage drop and its impact on performance will be quantified. A place and route engine (or another tool of a computer-aided design flow) will then take these timing considerations into account while performing partitioning of the device. A user's logic design is implemented into the logic array blocks taking into a voltage drop seen at those logic array blocks. Faster paths of the logic design are placed into faster logic array blocks, such as those in a core region of the integrated circuit.

    摘要翻译： 集成电路被分为两个或更多个不同的区域，每个区域是不同的电压域。 在每个区域，电压降及其对性能的影响将被量化。 然后，在执行设备分区时，会考虑到这些时间考虑因素，地方和路线引擎（或计算机辅助设计流程的另一个工具）将考虑这些时间考虑因素。 用户的逻辑设计被实现为在这些逻辑阵列块处看到的电压降的逻辑阵列块中。 将逻辑设计的更快的路径放置在更快的逻辑阵列块中，例如集成电路的核心区域中的那些。

    Power-driven timing analysis and placement for programmable logic
    6.
    发明授权
    Power-driven timing analysis and placement for programmable logic 有权
    用于可编程逻辑的功率驱动时序分析和放置

    公开(公告)号：US08099692B1

    公开(公告)日：2012-01-17

    申请号：US12953764

    申请日：2010-11-24

    申请人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    发明人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  Y02T10/82

    摘要： An integrated circuit is divided into two or more different regions, each region being a different voltage domain. In each of the regions, a voltage drop and its impact on performance will be quantified. A place and route engine (or another tool of a computer-aided design flow) will then take these timing considerations into account while performing partitioning of the device. A user's logic design is implemented into the logic array blocks taking into a voltage drop seen at those logic array blocks. Faster paths of the logic design are placed into faster logic array blocks, such as those in a core region of the integrated circuit.

    摘要翻译： 集成电路被分为两个或更多个不同的区域，每个区域是不同的电压域。 在每个区域，电压降及其对性能的影响将被量化。 然后，在执行设备分区时，会考虑到这些时间考虑因素，地方和路线引擎（或计算机辅助设计流程的另一个工具）将考虑这些时间考虑因素。 用户的逻辑设计被实现为在这些逻辑阵列块处看到的电压降的逻辑阵列块中。 将逻辑设计的更快的路径放置在更快的逻辑阵列块中，例如集成电路的核心区域中的那些。