公开(公告)号：US5963055A

公开(公告)日：1999-10-05

申请号：US810117

申请日：1997-02-25

申请人： Yasunori Tanaka ,  Ikue Yamamoto

发明人： Yasunori Tanaka ,  Ikue Yamamoto

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0948 ,  H03K19/0185

CPC分类号： H03K19/00315

摘要： A semiconductor output circuit serves as an interface circuit between LSIs having a high and a low supply voltages. The output circuit has at least a pre-buffer and an output stage circuit. The output stage circuit has a pull-up n-channel transistor arranged between an output pad and a low-voltage power source. The output pad may receive a high voltage from an external circuit, or the LSI operating with high supply voltage. The pre-buffer applies a voltage in the range of a ground voltage and a high voltage to the gate of the pull-up transistor, to turn on and off the pull-up transistor. The output stage circuit further has a reverse current prevention circuit formed between and connected to the low-voltage power source and the pull-up transistor, to block a reverse current flowing from the output pad to the low-voltage power source when the high voltage is applied to the output pad.

摘要翻译： 半导体输出电路用作具有高电源电压和低电源电压的LSI之间的接口电路。 输出电路至少具有预缓冲器和输出级电路。 输出级电路具有布置在输出焊盘和低压电源之间的上拉n沟道晶体管。 输出焊盘可以从外部电路接收高电压，或者以高电源电压工作的LSI。 预缓冲器将接地电压和高电压范围内的电压施加到上拉晶体管的栅极，以便导通和关断上拉晶体管。 输出级电路还具有形成在低电压电源和上拉晶体管之间并连接到低电压电源和上拉晶体管的反向电流防止电路，以在高电压时抑制从输出焊盘流向低压电源的反向电流 被施加到输出垫。

公开(公告)号：US5801550A

公开(公告)日：1998-09-01

申请号：US564499

申请日：1995-11-29

申请人： Yasunori Tanaka ,  Ikue Yamamoto

发明人： Yasunori Tanaka ,  Ikue Yamamoto

IPC分类号： H03K19/0175 ,  H03K17/16

CPC分类号： H03K17/167

摘要： The pulse output circuit device comprises two transistors (2, 4) for constructing an output buffer, a transistor (7) connected between the output line (OUTP) of the output buffer and the high potential supply voltage (VDD), a transistor (8) connected between the output line (OUT) of the output buffer and the low potential supply voltage (GND), a control circuit (39) for applying a gate signal to the transistor (7), and a control circuit (40) for applying a gate signal to the transistor (8). Whenever the signal level of the output buffer changes, the two control circuits (39, 40) turn on the transistor (7) or the transistor (8) for sharp level transition at the start of level transition, but turn on the transistor (7) or the transistor (8) on the basis of the relationship between the output level of the control circuit (39, 40) and the operating point of the transistor (7) or the transistor (8) at the end of level transition for absorption of the charge and discharge current to and from a parasitic capacitance (27). In the pulse output circuit device, it is possible to effectively prevent overshoot and undershoot caused when a pulse signal is outputted therethrough, while keeping the high output response speed and without increasing the circuit area.

摘要翻译： 脉冲输出电路装置包括用于构成输出缓冲器的两个晶体管（2,4），连接在输出缓冲器的输出线（OUTP）和高电位电源电压（VDD）之间的晶体管（7），晶体管（8） ），连接在输出缓冲器的输出线（OUT）和低电位电源电压（GND）之间，控制电路（39），用于向晶体管（7）施加栅极信号;以及控制电路（40） 到晶体管（8）的栅极信号。 每当输出缓冲器的信号电平变化时，两个控制电路（39,40）在电平转换开始时导通晶体管（7）或晶体管（8）以进行尖锐的电平转换，而导通晶体管（7 ）或晶体管（8），基于控制电路（39,40）的输出电平与晶体管（7）或晶体管（8）在电平转换结束时的吸收的操作点之间的关系 的来自寄生电容（27）的充放电电流。 在脉冲输出电路装置中，在保持高输出响应速度且不增加电路面积的同时，可以有效地防止在输出脉冲信号时引起的过冲和下冲。