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公开(公告)号:US4870659A
公开(公告)日:1989-09-26
申请号:US237535
申请日:1988-08-29
IPC分类号: H04L27/152
CPC分类号: H04L27/1525
摘要: An FSK demodulation circuit which receives as input an FSK modulated reception signal, obtains two quadrature pulse trains, i.e., a first pulse train and a second pulse train, from a phase detection circuit, is provided with at least two sampling means which use the edge of one of the pulse trains and sample the logic of the other pulse train, produces two or more sample outputs at different timings, and determines the logic of the reproduced data from a combination of the logics "1" and "0" of the sample outputs.