公开(公告)号：US06795344B2

公开(公告)日：2004-09-21

申请号：US10316851

申请日：2002-12-12

Applicant: Yeh Jun Lin

Inventor： Yeh Jun Lin

IPC: G11C1610

CPC classification number: G11C16/30

Abstract: A floating gate memory architecture having current regulator is disclosed. A floating gate memory block have at least a programming voltage node for being programmed a plurality of bits according to the control of a plurality of bit lines. A high voltage source provides a regulated voltage when the plurality of bits are programmed in. A high voltage decoder locates between the floating gate memory block and the high voltage source for connecting the voltage to the programming voltage node according to the programming data of the floating gate memory block. A current regulator connects to the programming voltage node for keeping the programming voltage node in a constant voltage, and making a constant current flowing into said floating gate memory block according to said plurality of bits.

Abstract translation: 公开了一种具有电流调节器的浮动存储架构。 浮动栅极存储块至少具有编程电压节点，用于根据多个位线的控制来编程多个位。 当多个位被编程时，高电压源提供调节电压。高电压解码器位于浮动栅极存储器块和高电压源之间，用于根据浮动的编程数据将电压连接到编程电压节点 门内存块。 电流调节器连接到编程电压节点，用于将编程电压节点保持在恒定电压，并根据所述多个位使恒定电流流入所述浮动栅极存储器块。