公开(公告)号：US06834058B1

公开(公告)日：2004-12-21

申请号：US09751568

申请日：2000-12-29

申请人： Yehuda Moyal ,  Yehezkel Levi

发明人： Yehuda Moyal ,  Yehezkel Levi

IPC分类号： H04J306

CPC分类号： H04L49/9094 ,  H04L25/14 ,  H04L49/90

摘要： A novel and useful mechanism of synchronizing and aligning a plurality of data streams. The invention comprises a plurality of sync machines and an alignment circuit which in combination function to synchronize and align multiple variable length cell streams. Each sync machine is operative to control the output clocking of a corresponding FIFO queue. The data stream output of each FIFO queue is monitored by a sync machine and all the sync machines are coupled to the alignment circuit. In operation, the sync machines synchronize to the cells by searching for the error checks sequence (ECS) at the end of each cell. Upon synchronization being achieved for all the data streams, the alignment circuit causes each sync machine to freeze its respective FIFO until the ECS arrives on the data stream most delayed in time. Once the ECS is received on the slowest data stream, the alignment circuit releases the hold and consequently the FIFOs are released by the sync machines.

摘要翻译： 一种同步和对齐多个数据流的新颖有用的机制。 本发明包括多个同步机和对准电路，其组合起来能够同步和对准多个可变长度的单元流。 每个同步机可操作以控制对应的FIFO队列的输出时钟。 每个FIFO队列的数据流输出由同步机监视，并且所有同步机耦合到对准电路。 在操作中，同步机器通过搜索每个单元末端的错误检查序列（ECS）与单元同步。 在对所有数据流实现同步时，对准电路使每个同步机冻结其各自的FIFO，直到ECS到达数据流最为延迟的时间。 一旦在最慢的数据流上接收到ECS，对准电路释放保持，因此FIFO被同步器释放。

公开(公告)号：US06807638B1

公开(公告)日：2004-10-19

申请号：US09751428

申请日：2000-12-29

申请人： Yehuda Moyal ,  Yehezkel Levi ,  Ilan Glaser ,  Simon Grinberg

发明人： Yehuda Moyal ,  Yehezkel Levi ,  Ilan Glaser ,  Simon Grinberg

IPC分类号： H04L700

CPC分类号： H04J3/0685 ,  H04J3/062

摘要： A novel and useful apparatus for and method of in-band clock compensation for use in synchronous communication systems. The clock compensation mechanism is implemented in each module and is operative to compensate for the differences between the clocks among the various modules in the system. The mechanism operates in band wherein special clock compensation symbols are periodically inserted into the data stream itself. Additional clock sync symbols are added to the data stream depending on the current level of the FIFO queue on the module or card. The insertion (or non-insertion) of additional symbols functions to compensate for the faster (or slower) clock of the module when compared to that of the reference.

摘要翻译： 一种用于同步通信系统中的带内时钟补偿的新颖有用的装置和方法。 时钟补偿机制在每个模块中实现，并且可用于补偿系统中各个模块之间的时钟之间的差异。 该机制在频带中操作，其中特殊时钟补偿符号被周期性地插入到数据流本身中。 根据模块或卡上的FIFO队列的当前级别，将额外的时钟同步符号添加到数据流。 附加符号的插入（或非插入）用于补偿与参考值相比更快（或更慢）的模块时钟。

公开(公告)号：US06445680B1

公开(公告)日：2002-09-03

申请号：US09085341

申请日：1998-05-27

申请人： Yehuda Moyal

发明人： Yehuda Moyal

IPC分类号： H04L1228

CPC分类号： H04L49/9031 ,  H04L12/5601 ,  H04L47/10 ,  H04L47/266 ,  H04L49/90 ,  H04L49/901 ,  H04L2012/5679 ,  H04L2012/5681

摘要： An arbiter utilizing a link list to arbitrate access between multiple data sources and a single destination. The arbiter is of the least recently used type whereby the data source that has not sent data for the longest time is given the highest priority. The arbiter provides an arbitration function in a simple manner and at high speeds. The arbiter utilizes a Non Empty Source Queue (NESQ) list that comprises only sources that are non empty, i.e., that have data ready to send. If a source queue chosen for data transmission still has data to send, it is placed at the end of the NESQ list. When a source queue becomes empty after the transmission of data, the source index is removed from the linked list. Conversely, when a source queue that was previously empty receives a new packet it is added to the end of the linked list.

摘要翻译： 仲裁器利用链路列表仲裁多个数据源和单个目的地之间的访问。 仲裁器是最近最少使用的类型，由此最长时间没有发送数据的数据源被赋予最高优先级。 仲裁器以简单的方式和高速度提供仲裁功能。 仲裁器利用非空源队列（NESQ）列表，其中仅包含非空的源，即具有准备发送的数据的源。 如果为数据传输选择的源队列仍具有要发送的数据，则将其放置在NESQ列表的末尾。 在数据传输后源队列变为空时，将从链表中删除源索引。 相反，当以前为空的源队列接收到新的数据包时，它将被添加到链表的末尾。

公开(公告)号：US06430198B1

公开(公告)日：2002-08-06

申请号：US08970545

申请日：1997-11-14

申请人： Yehuda Moyal ,  Ilan Glaser

发明人： Yehuda Moyal ,  Ilan Glaser

IPC分类号： H04J324

CPC分类号： H04L47/10 ,  H04L47/36

摘要： An apparatus for and a method of reducing the packet length count processing of data packets in a network device. The apparatus and method determine the length and end of a packet at the ingress point of the network computing device, e.g., a switch or router, using a single counting function. After the counting function verifies the length of the data packet, a signal indicating the length of a data packet is generated. This packet length indicator signal is then propagated throughout the system along with the data packet itself. The packet length indicator signal is then used at all decision points that involve the data packet. The packet length indicator signal itself is generated so as to indicate the beginning of the start of the data packet in addition to the end of the data packet, thus indicating the length of the packet. This obviates the need for the length of the packet to be counted over and over again in the course of processing the data packet within the switch or router.

摘要翻译： 一种用于减少网络设备中的数据分组的分组长度计数处理的装置和方法。 该装置和方法使用单个计数功能来确定网络计算设备（例如交换机或路由器）的入口点处的分组的长度和结束。 在计数功能验证数据包的长度之后，生成指示数据包的长度的信号。 然后，该数据包长度指示符信号与数据包本身一起在整个系统中传播。 然后在涉及数据分组的所有决策点使用分组长度指示符信号。 生成分组长度指示符信号本身，以便除了数据分组的结束之外还指示数据分组的开始开始，从而指示分组的长度。 这样就不需要在处理交换机或路由器内的数据包的过程中一次又一次地对数据包的长度进行计数。