公开(公告)号：US20100096629A1

公开(公告)日：2010-04-22

申请号：US12254156

申请日：2008-10-20

Applicant: Yeow Chyi CHEN

Inventor： Yeow Chyi CHEN

IPC: H01L25/065

CPC classification number: G11C29/32 ,  G11C5/04 ,  H01L25/065 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention provides a multi-chip module. In one embodiment, the multi-chip module comprises a serial flash die and a primary die, and the primary die comprises a built-in self-test controller and a serial flash controller. The built-in self-test controller generates a write command to write first data to a memory location of the serial flash die, generates a read command to read second data from the memory location of the serial flash die, and compares the second data with the first data to determine whether the memory location is defective for generating failed address information about the serial flash die. The serial flash controller accesses the serial flash die according to the write command and the read command.

Abstract translation: 本发明提供一种多芯片模块。 在一个实施例中，多芯片模块包括串行闪存管芯和主管芯，并且主管芯包括内置的自检控制器和串行闪存控制器。 内置的自检控制器产生一个写入命令，将第一个数据写入到串行闪存芯片的存储器位置，产生读取命令，从串行闪存芯片的存储单元读取第二个数据，并将第二个数据与 用于确定存储器位置是否有缺陷以产生关于串行闪存芯片的失败地址信息的第一数据。 串行闪存控制器根据写入命令和读取命令访问串行闪存芯片。