-
公开(公告)号：US20240120016A1
公开(公告)日：2024-04-11
申请号：US18392740
申请日：2023-12-21
发明人： Devanathan Varadarajan , Lei Wu
IPC分类号： G11C29/16 , G01R31/3185 , G11C29/02 , G11C29/10 , G11C29/12 , G11C29/14 , G11C29/26 , G11C29/32 , G11C29/36
CPC分类号： G11C29/16 , G01R31/318594 , G01R31/318597 , G11C29/022 , G11C29/023 , G11C29/10 , G11C29/1201 , G11C29/12015 , G11C29/14 , G11C29/26 , G11C29/32 , G11C29/36
摘要： Methods to test functional memory interface logic of a core under test utilize a built-in-self-test (BIST) controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at BIST mode, an at-speed functional mode is utilized to capture a desired memory output.
-
公开(公告)号：US20240071549A1
公开(公告)日：2024-02-29
申请号：US17822909
申请日：2022-08-29
发明人： Sujeet Ayyapureddi
CPC分类号： G11C29/42 , G11C7/1069 , G11C29/32
摘要： Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.
-
公开(公告)号：US11848066B2
公开(公告)日：2023-12-19
申请号：US17714136
申请日：2022-04-05
发明人： Ket Chong Yap , Chihhung Liao , Shieh Huan Yen
IPC分类号： G11C29/32 , G11C29/20 , G11C29/12 , H03K19/173 , H03K19/17728
CPC分类号： G11C29/32 , G11C29/1201 , G11C29/20 , H03K19/1737 , H03K19/17728 , G11C2029/1202 , G11C2029/1204 , G11C2029/3202
摘要： A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.
-
公开(公告)号：US20230317192A1
公开(公告)日：2023-10-05
申请号：US17714136
申请日：2022-04-05
发明人： Ket Chong Yap , Chihhung Liao , Shieh Huan Yen
IPC分类号： G11C29/32 , G11C29/20 , G11C29/12 , H03K19/17728 , H03K19/173
CPC分类号： G11C29/32 , G11C29/20 , G11C29/1201 , H03K19/17728 , H03K19/1737 , G11C2029/1204 , G11C2029/3202 , G11C2029/1202
摘要： A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.
-
公开(公告)号：US11756646B2
公开(公告)日：2023-09-12
申请号：US17541645
申请日：2021-12-03
发明人： Taekwoon Kim , Wonhyung Song , Jangseok Choi
CPC分类号： G11C29/42 , G11C29/12015 , G11C29/32 , G11C29/44 , G11C2029/1206 , G11C2029/4402
摘要： A memory system includes a memory module and a memory controller. The memory module includes data chips that store data and are assigned to a first sub-channel that generates a first code word or a second sub-channel that generates a second code word, where the first code word and the second code are used to fill a single cache line. The memory controller, upon detection of a hard-fail data chip among the data chips, copies data from the hard-fail data chip to the ECC chip, releases mapping between the hard-fail data chip and corresponding I/O, and defines new mapping between the ECC chip and the corresponding I/O pins.
-
公开(公告)号：US11749369B2
公开(公告)日：2023-09-05
申请号：US17943156
申请日：2022-09-12
发明人： Antonino Mondello , Alberto Troia
CPC分类号： G11C29/32 , G01R31/2815 , G11C7/06 , G11C29/16 , G11C29/42 , G11C2029/3202
摘要： The present disclosure relates to an apparatus comprising a non-volatile memory architecture configured to be coupled to a System-on-Chip (SoC) device. The non-volatile memory device coupled to the SoC having a structurally independent structure linked to the SoC includes a plurality of sub arrays forming a matrix of memory cells with associated decoding and sensing circuitry, sense amplifiers coupled to a corresponding sub array, a data buffer comprising a plurality of JTAG cells coupled to outputs of the sense amplifiers; and a scan-chain connecting together the JTAG cells of the data buffer.
-
公开(公告)号：US11694758B2
公开(公告)日：2023-07-04
申请号：US17397853
申请日：2021-08-09
CPC分类号： G11C29/32 , G11C16/3495 , G11C29/4401 , G11C29/46
摘要： Exemplary methods, apparatuses, and systems include receiving a plurality of read operations. The read operations are divided into a current set of a sequence of read operations and one or more other sets. The size of the current set is a first number of read operations. An aggressor read operation is selected from the current set. A data integrity scan is performed on a victim of the aggressor and a first indicator of data integrity is determined based on the first data integrity scan. A size of a subsequent set of read operations is set to a second number, which less than the first number, based on the indicator of data integrity.
-
8.发明申请公开(公告)号：US20190004114A1
公开(公告)日：2019-01-03
申请号：US15636793
申请日：2017-06-29
申请人： GLOBALFOUNDRIES INC.
发明人： JIAN SUN , CHAO MENG , XIAOXIAO LI , YINPENG LU
IPC分类号： G01R31/3185 , G11C29/30 , G06F11/22 , H03K19/177 , H03K19/173
CPC分类号： G01R31/318536 , G01R31/318505 , G06F11/2205 , G11C29/12015 , G11C29/30 , G11C29/32 , G11C2029/3202 , H03K19/1735 , H03K19/1776
摘要： A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal.
-
公开(公告)号：US20180294042A1
公开(公告)日：2018-10-11
申请号：US15974033
申请日：2018-05-08
CPC分类号： G11C29/023 , G11C7/1012 , G11C7/20 , G11C7/22 , G11C29/12015 , G11C29/32 , G11C2029/0407 , G11C2029/3202
摘要： Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
-
公开(公告)号：US20180246796A1
公开(公告)日：2018-08-30
申请号：US15442039
申请日：2017-02-24
申请人： Intel Corporation
CPC分类号： G06F11/277 , G06F11/221 , G06F11/2221 , G06F13/1668 , G06F13/385 , G06F13/4022 , G06F13/4282 , G06F2213/0026 , G11C29/1201 , G11C29/32 , G11C29/38
摘要： Embodiments are generally directed to a mechanism to provide back-to-back testing of memory controller operation. An embodiment of an apparatus includes a test controller including a specialized self-testing mechanism for memory control testing, the memory control testing including testing with back-to-back transactions; and a memory controller, the memory controller including one or more transaction arbiters, one or more arbiter queues for memory transactions, an auto response mechanism to provide a response to a read transaction, and a switching mechanism to switch the memory control between a functional mode and an auto response mode. The test controller is to generate test transactions and transfer the test transactions to the memory controller. The memory controller is to block the one or more transaction arbiters, place the plurality of test transactions in the one or more arbiter queues, and to unblock the transaction arbiters upon an event.
-
-
-
-
-
-
-
-
-
搜索结果
562 条记录 (耗时 0.024 秒)
