公开(公告)号：US20090248934A1

公开(公告)日：2009-10-01

申请号：US12412286

申请日：2009-03-26

申请人： Yi Ge ,  ChaoJun Liu ,  Wen Bo Shen ,  Yuan Ping

发明人： Yi Ge ,  ChaoJun Liu ,  Wen Bo Shen ,  Yuan Ping

IPC分类号： G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/505

摘要： Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor.

摘要翻译： 公开了一种多核处理器环境中的中断调度系统和方法。 该处理器包括中断调度器和能够进行中断处理的N个核，其被分成多组核心，其中N是大于1的正整数。 该方法响应于到达中断产生令牌; 根据中断，确定要优先用于处理中断的一组核心作为热组; 并将令牌发送到热组，从热组中的第一核心顺序地确定是否满足中断分派终止条件，并且在确定中断满足时将当前核心确定为用于处理中断的响应核心 调度终止条件。 利用本发明，减少了处理器对中断的响应延迟，从而提供了处理器的优化性能。

公开(公告)号：US07953915B2

公开(公告)日：2011-05-31

申请号：US12412286

申请日：2009-03-26

申请人： Yi Ge ,  ChaoJun Liu ,  Wen Bo Shen ,  Yuan Ping

发明人： Yi Ge ,  ChaoJun Liu ,  Wen Bo Shen ,  Yuan Ping

IPC分类号： G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/505

摘要： Disclosed is an interrupt dispatching system and method in a multi-core processor environment. The processor includes an interrupt dispatcher and N cores capable of interrupt handling which are divided into a plurality of groups of cores, where N is a positive integer greater than one. The method generates a token in response to an arriving interrupt; determines a group of cores to be preferentially used to handle the interrupt as a hot group in accordance with the interrupt; and sends the token to the hot group, determines sequentially from the first core in the hot group whether an interrupt dispatch termination condition is satisfied, and determines the current core as a response core to be used to handle the interrupt upon determining satisfaction of the interrupt dispatch termination condition. With the invention, delay in responding to an interrupt by the processor is reduced providing optimized performance of the processor.

摘要翻译： 公开了一种多核处理器环境中的中断调度系统和方法。 该处理器包括中断调度器和能够进行中断处理的N个核，其被分成多组核心，其中N是大于1的正整数。 该方法响应于到达中断产生令牌; 根据中断，确定要优先用于处理中断的一组核心作为热组; 并将令牌发送到热组，从热组中的第一核心顺序地确定是否满足中断分派终止条件，并且在确定中断满足时将当前核心确定为用于处理中断的响应核心 调度终止条件。 利用本发明，减少了处理器对中断的响应延迟，从而提供了处理器的优化性能。