公开(公告)号：US20120278776A1

公开(公告)日：2012-11-01

申请号：US13416642

申请日：2012-03-09

申请人： Cheok-Kei LEI ,  Yi-Tang LIN ,  Hsiao-Hui CHEN ,  Yu-Ning CHANG ,  Shu-Yu CHEN ,  Chien-Wen CHEN ,  Chih-Sheng CHANG ,  Clement Hsingjen WANN

发明人： Cheok-Kei LEI ,  Yi-Tang LIN ,  Hsiao-Hui CHEN ,  Yu-Ning CHANG ,  Shu-Yu CHEN ,  Chien-Wen CHEN ,  Chih-Sheng CHANG ,  Clement Hsingjen WANN

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  G06F17/5068 ,  H01L21/823821

摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated.

摘要翻译： 公开了一种用于从具有平面晶体管的器件的第一布局生成具有FinFET的器件的布局的方法。 分析平面布局并生成相应的FinFET结构。

公开(公告)号：US20120278777A1

公开(公告)日：2012-11-01

申请号：US13416742

申请日：2012-03-09

申请人： Yi-Tang LIN ,  Cheok-Kei LEI ,  Shu-Yu CHEN ,  Yu-Ning CHANG ,  Hsiao-Hui CHEN ,  Chih-Sheng CHANG ,  Chien-Wen CHEN ,  Clement Hsingjen WANN

发明人： Yi-Tang LIN ,  Cheok-Kei LEI ,  Shu-Yu CHEN ,  Yu-Ning CHANG ,  Hsiao-Hui CHEN ,  Chih-Sheng CHANG ,  Chien-Wen CHEN ,  Clement Hsingjen WANN

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5068 ,  H01L21/823821 ,  H01L27/0207

摘要： A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted.

公开(公告)号：US20130091483A1

公开(公告)日：2013-04-11

申请号：US13326670

申请日：2011-12-15

申请人： Hsiao-Hui CHEN ,  Shiue Tsong SHEN ,  Cheok-Kei LEI

发明人： Hsiao-Hui CHEN ,  Shiue Tsong SHEN ,  Cheok-Kei LEI

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/505 ,  G06F2217/84

摘要： A method and system optimizes or improves an electronic design by analyzing various signal paths in the electronic design and selecting certain critical paths, for example, failed-timing paths, to optimize. The optimizing method extracts the cascaded logic gates to create a megacell representing the function of the critical path, compare test parameters of the megacell with the critical path, and incorporate the megacell into the electronic design if the test parameters improve by an optimizing constraint.

摘要翻译： 一种方法和系统通过分析电子设计中的各种信号路径并选择某些关键路径（例如，故障定时路径）进行优化来优化或改进电子设计。 优化方法提取级联逻辑门，以创建代表关键路径功能的巨型电位器，将大型电池的测试参数与关键路径进行比较，并且如果测试参数通过优化约束改进，则将大电流器并入电子设计。