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公开(公告)号：US06988207B2
公开(公告)日：2006-01-17
申请号：US09882960
申请日：2001-06-15
CPC分类号： G01R31/318552 , G01R31/318572 , G01R31/318594
摘要： A circuit that uses a bi-directional buffer as follows: First a tri-state output buffer is connected to a functional clock and a bi-directional port is connected to a test clock. The bi-directional buffer is configured to receive control signals to selectively block and unblock the tri-state output port connected to the functional clock. In addition, the bi-directional port connected to a test clock is connected to the internal logic of the device. When the tri-state output buffer connected to the functional clock is blocked, the test clock transmits a clock signal to the internal logic of the device. When the tri-state output buffer connected to the functional clock is unblocked, the functional clock transmits a clock signal to the internal logic of the device.
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2.发明授权Method of using testbench tests to avoid task collisions in hardware description language 有权使用测试台测试来避免硬件描述语言中的任务冲突的方法公开(公告)号：US06701494B2
公开(公告)日：2004-03-02
申请号：US10137846
申请日：2002-05-01
申请人： L. Grant Giddens , Ronald R. Munoz
发明人： L. Grant Giddens , Ronald R. Munoz
IPC分类号： G06F1750
CPC分类号： G01R31/318357 , G01R31/318314 , G01R31/318364 , G06F17/5022
摘要： A method and system for performing simultaneous tests and avoiding task collisions using a hardware description language includes designating a timeslot for one or more of the simultaneous tests, associating the designated timeslot with one or more of the tasks to be performed in a test, determining if the designated timeslot is available before executing the tasks associated with timeslots and executing the tasks when the designated timeslots become available.
摘要翻译： 一种用于执行同时测试并且避免使用硬件描述语言的任务冲突的方法和系统包括指定一个或多个同时测试的时隙，将所指定的时隙与要在测试中执行的任务中的一个或多个相关联，确定是否 在执行与时隙相关的任务并在指定的时隙可用时执行任务，指定的时隙可用。
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公开(公告)号：US07142592B2
公开(公告)日：2006-11-28
申请号：US10137246
申请日：2002-04-30
IPC分类号： H04B17/00
CPC分类号： H04L25/0262
摘要： A device for determining speeds of a digital signal in a serial transmission line. The device comprises a first and second counter and a logic circuit. The first counter is adapted to count the duration of a first pulse in a first byte of the digital signal in the transmission line. The second counter is adapted to count the duration of a second pulse in the first byte. The logic circuit is coupled to the first and second counters. The logic circuit is adapted to compare the smallest duration of the first and second pulses with a plurality of pulse duration's of known baud rates to determine the baud rate of the digital signal in the transmission line.
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