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    Plasma display, and driving device and method thereof
    3.
    发明申请
    Plasma display, and driving device and method thereof 审中-公开
    等离子显示器及其驱动装置及其方法

    公开(公告)号：US20080068366A1

    公开(公告)日：2008-03-20

    申请号：US11892547

    申请日：2007-08-23

    Applicant: Joon-Yeon Kim ,  Yong-Jin Jeong

    Inventor： Joon-Yeon Kim ,  Yong-Jin Jeong

    IPC: G06F3/038 ,  G09G5/00

    CPC classification number: G09G3/2965

    Abstract: In a plasma display device, a driver circuit and a method of driving that reduces costs by eliminating the need for high voltage transistors. A first terminal of an inductor is coupled to a plurality of first electrodes. A first terminal of a first capacitor is coupled to the first terminal of the inductor, a second terminal of the first capacitor is coupled to the plurality of first electrodes, a first terminal of a second capacitor is coupled to the first terminal of the inductor, and a second terminal of the second capacitor is coupled to the plurality of first electrodes. In addition, a resonance path for varying a voltage at the plurality of first electrodes is formed between a node of the first and second capacitors and the plurality of first electrodes. Further, a power source for supplying a first voltage is coupled to a first terminal of a first transistor, a first terminal of a second transistor is coupled to a second terminal of the first transistor, and a second terminal of a third transistor including a first terminal coupled to a second terminal of the second transistor is coupled to a power source for supplying a second voltage that is lower than the first voltage. The second terminal of the first transistor is coupled to the second terminal of the first capacitor, and the first terminal of the third transistor is coupled to the second terminal of the second capacitor.

    Abstract translation: 在等离子体显示装置中，驱动电路和驱动方法通过消除对高压晶体管的需要来降低成本。 电感器的第一端子耦合到多个第一电极。 第一电容器的第一端子耦合到电感器的第一端子，第一电容器的第二端子连接到多个第一电极，第二电容器的第一端子耦合到电感器的第一端子， 并且第二电容器的第二端子耦合到多个第一电极。 此外，在第一和第二电容器的节点与多个第一电极之间形成用于改变多个第一电极处的电压的谐振路径。 此外，用于提供第一电压的电源耦合到第一晶体管的第一端子，第二晶体管的第一端子耦合到第一晶体管的第二端子，第三晶体管的第二端子包括第一晶体管， 耦合到第二晶体管的第二端子的端子耦合到用于提供低于第一电压的第二电压的电源。 第一晶体管的第二端子耦合到第一电容器的第二端子，并且第三晶体管的第一端子耦合到第二电容器的第二端子。

    Device and method for modular multiplication
    4.
    发明授权
    Device and method for modular multiplication 失效
    用于模数乘法的装置和方法

    公开(公告)号：US6151393A

    公开(公告)日：2000-11-21

    申请号：US085963

    申请日：1998-05-27

    Applicant: Yong-Jin Jeong

    Inventor： Yong-Jin Jeong

    IPC: G06F7/496 ,  G06F7/44 ,  G06F7/53 ,  G06F7/72 ,  G09C1/00 ,  G06F7/38

    CPC classification number: G06F7/722

    Abstract: A method and apparatus are disclosed for performing modular multiplication. Modular multiplication in accordance with the present invention includes precalculating a 2's complement of a given modulus and multiples of the 2's complement and calculating a total magnitude of end-around carries during the modular multiplication. The calculated multiples are selected depending on the total magnitude of the end-around carries, and the selected multiples are added. The disclosure includes array structures in accordance with the present invention. The invention includes an algorithm designed for Rivest-Shamir-Adelman (RSA) cryptography and based on the familiar iterative Homer's rule, but uses precalculated complements of the modulus. The problem of deciding which multiples of the modulus to subtract in intermediate iteration stages has been simplified using simple look-up of precalculated complement numbers, thus allowing a finer-grain pipeline. Regularity and local connections make the algorithm suitable for high-performance array implementation in FPGA's (field programmable gate arrays) or deep submicron VLSI's.

    Abstract translation: 公开了用于执行模乘法的方法和装置。 根据本发明的模块化乘法包括预先计算给定模量的2的补数和2的补码的倍数，并在模乘期间计算终端携带的总量值。 根据终端携带的总量选择计算出的倍数，并添加选定的倍数。 本公开包括根据本发明的阵列结构。 本发明包括为Rivest-Shamir-Adelman（RSA）密码学设计的算法，并且基于熟悉的迭代荷马规则，但是使用模数的预先计算的补码。 通过使用预先计算的补码数的简单查找，可以简化决定在中间迭代阶段减去哪个倍数的模数的问题，从而允许更细粒度的管道。 规则和本地连接使得该算法适用于FPGA（现场可编程门阵列）或深亚微米VLSI中的高性能阵列实现。

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