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    Flash memory device for determining most significant bit program
    1.
    发明授权
    Flash memory device for determining most significant bit program 失效
    用于确定最高有效位程序的闪存设备

    公开(公告)号：US07894258B2

    公开(公告)日：2011-02-22

    申请号：US12188057

    申请日：2008-08-07

    申请人： Yong-Taek Jeong ,  Sang-Chul Kang ,  Kyong-Ae Kim

    发明人： Yong-Taek Jeong ,  Sang-Chul Kang ,  Kyong-Ae Kim

    IPC分类号： G11C11/34

    CPC分类号： G11C11/5621 ,  G11C7/1006 ,  G11C16/3454 ,  G11C2211/5646

    摘要： A flash memory device capable of efficiently determining whether most significant bit (MSB) programming has been performed is provided. The flash memory device includes a cell array, a control unit, and a determination unit. The cell array includes at least one flag cell for storing information about whether MSB programming has been performed on a multi-level cell. The control unit controls a program operation, a read operation, and an erasure operation with respect to the cell array. The determination unit receives flag data stored in the flag cells, performs an OR operation and/or an AND operation on the flag data, and generates a determination signal based on a result of the OR operation and/or the AND operation, wherein the determination signal represents whether the MSB programming has been performed.

    摘要翻译： 提供能够有效地确定是否执行最高有效位（MSB）编程的快闪存储器件。 闪存器件包括单元阵列，控制单元和确定单元。 单元阵列包括至少一个标志单元，用于存储关于是否在多级单元上执行了MSB编程的信息。 控制单元控制关于单元阵列的程序操作，读取操作和擦除操作。 确定单元接收存储在标志单元中的标志数据，对标志数据执行“或”运算和/或“与”运算，并且基于“或”运算和/或“与”运算的结果生成确定信号，其中确定 信号表示是否已经执行了MSB编程。

    Flash Memory Device for Determining Most Significant Bit Program
    2.
    发明申请
    Flash Memory Device for Determining Most Significant Bit Program 失效
    用于确定最重要位程序的闪存设备

    公开(公告)号：US20090147574A1

    公开(公告)日：2009-06-11

    申请号：US12188057

    申请日：2008-08-07

    申请人： Yong Taek Jeong ,  Sang-Chul Kang ,  Kyong-Ae Kim

    发明人： Yong Taek Jeong ,  Sang-Chul Kang ,  Kyong-Ae Kim

    IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/00

    CPC分类号： G11C11/5621 ,  G11C7/1006 ,  G11C16/3454 ,  G11C2211/5646

    摘要： A flash memory device capable of efficiently determining whether most significant bit (MSB) programming has been performed is provided. The flash memory device includes a cell array, a control unit, and a determination unit. The cell array includes at least one flag cell for storing information about whether MSB programming has been performed on a multi-level cell. The control unit controls a program operation, a read operation, and an erasure operation with respect to the cell array. The determination unit receives flag data stored in the flag cells, performs an OR operation and/or an AND operation on the flag data, and generates a determination signal based on a result of the OR operation and/or the AND operation, wherein the determination signal represents whether the MSB programming has been performed.

    摘要翻译： 提供能够有效地确定是否执行最高有效位（MSB）编程的快闪存储器件。 闪存器件包括单元阵列，控制单元和确定单元。 单元阵列包括至少一个标志单元，用于存储关于是否在多级单元上执行了MSB编程的信息。 控制单元控制关于单元阵列的程序操作，读取操作和擦除操作。 确定单元接收存储在标志单元中的标志数据，对标志数据执行“或”运算和/或“与”运算，并且基于“或”运算和/或“与”运算的结果生成确定信号，其中确定 信号表示是否已经执行了MSB编程。

    Memory card using NAND flash memory and its operating method
    4.
    发明授权
    Memory card using NAND flash memory and its operating method 失效
    存储卡采用NAND闪存及其操作方法

    公开(公告)号：US07356646B2

    公开(公告)日：2008-04-08

    申请号：US11025731

    申请日：2004-12-28

    申请人： Kyong-Ae Kim

    发明人： Kyong-Ae Kim

    IPC分类号： G06F9/26 ,  G06F9/34 ,  G06F12/06 ,  G06F12/00 ,  G11C11/34 ,  G11C16/04 ,  H05K7/10

    CPC分类号： G06F13/1694

    摘要： A memory card is connected to a host using a NAND flash memory interface mode. In addition, the memory card further includes the NAND flash memory as well as a controller. The NAND flash memory uses an interface mode different from that supported by the host. The controller converts the interface mode of the host to the interface mode of the NAND flash memory. Thus a memory card can be made compatible with a host using another interface mode.

    摘要翻译： 使用NAND闪存接口模式将存储卡连接到主机。 此外，存储卡还包​​括NAND闪存以及控制器。 NAND闪存使用与主机不同的接口模式。 控制器将主机的接口模式转换为NAND闪存的接口模式。 因此，可以使用另一种接口模式使存储卡与主机兼容。

    Memory card providing hardware acceleration for read operations
    5.
    发明授权
    Memory card providing hardware acceleration for read operations 有权
    存储卡为读操作提供硬件加速

    公开(公告)号：US07555629B2

    公开(公告)日：2009-06-30

    申请号：US11321870

    申请日：2005-12-30

    申请人： Kyong-Ae Kim ,  Jong-Yeol Park ,  Dong-Hee Lee

    发明人： Kyong-Ae Kim ,  Jong-Yeol Park ,  Dong-Hee Lee

    IPC分类号： G06F12/00

    CPC分类号： G06F13/385

    摘要： A memory card comprises a memory controller connected to a non-volatile memory module. The memory controller comprises a first circuit adapted to convert a first external address into a first internal address using a program stored in an internal memory. The memory controller further comprises a hardware accelerator adapted to generate a second internal address based on the first internal and external addresses.

    摘要翻译： 存储卡包括连接到非易失性存储器模块的存储器控​​制器。 存储器控制器包括适于使用存储在内部存储器中的程序将第一外部地址转换为第一内部地址的第一电路。 存储器控制器还包括适于基于第一内部和外部地址产生第二内部地址的硬件加速器。

    Memory card using NAND flash memory and its operating method
    6.
    发明申请
    Memory card using NAND flash memory and its operating method 失效
    存储卡采用NAND闪存及其操作方法

    公开(公告)号：US20050207231A1

    公开(公告)日：2005-09-22

    申请号：US11025731

    申请日：2004-12-28

    申请人： Kyong-Ae Kim

    发明人： Kyong-Ae Kim

    IPC分类号： G06K19/07 ,  G06F3/08 ,  G06F13/14 ,  G11C11/34 ,  G11C16/00

    CPC分类号： G06F13/1694

    摘要： A memory card is connected to a host using a NAND flash memory interface mode. In addition, the memory card further includes the NAND flash memory as well as a controller. The NAND flash memory uses an interface mode different from that supported by the host. The controller converts the interface mode of the host to the interface mode of the NAND flash memory. Thus a memory card can be made compatible with a host using another interface mode.

    摘要翻译： 使用NAND闪存接口模式将存储卡连接到主机。 此外，存储卡还包​​括NAND闪存以及控制器。 NAND闪存使用与主机不同的接口模式。 控制器将主机的接口模式转换为NAND闪存的接口模式。 因此，可以使用另一种接口模式使存储卡与主机兼容。

    Incremental merge methods and memory systems using the same
    7.
    发明授权
    Incremental merge methods and memory systems using the same 失效
    增量合并方法和使用相同的内存系统

    公开(公告)号：US07529879B2

    公开(公告)日：2009-05-05

    申请号：US10990065

    申请日：2004-11-16

    申请人： Jin-Hyuk Kim ,  Chan-Ik Park ,  Young-Gon Kim ,  Kyong-Ae Kim

    发明人： Jin-Hyuk Kim ,  Chan-Ik Park ,  Young-Gon Kim ,  Kyong-Ae Kim

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F2212/7205

    摘要： Memory systems and methods of controlling a flash memory are provided that execute one of a plurality of merge stages of an incremental merge operation responsive to receiving a command to the flash memory. Executing one of a plurality of merge stages may include receiving a command to the flash memory, determining whether the flash memory is executing an incremental merge operation and executing a next merge stage of the incremental merge operation if the flash memory is executing an incremental merge operation.

    摘要翻译： 提供了控制闪速存储器的存储器系统和方法，其响应于接收到闪速存储器的命令而执行增量合并操作的多个合并级中的一个。 执行多个合并阶段中的一个可以包括：如果闪存正在执行增量合并操作，则向闪存接收命令，确定闪存是否正在执行增量合并操作并执行增量合并操作的下一个合并阶段 。

    Memory card and method for storing data on memory card
    9.
    发明授权
    Memory card and method for storing data on memory card 有权
    存储卡和存储卡上数据的方法

    公开(公告)号：US08321633B2

    公开(公告)日：2012-11-27

    申请号：US11833585

    申请日：2007-08-03

    申请人： Kyong-Ae Kim

    发明人： Kyong-Ae Kim

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1673

    摘要： A memory card, connected to a host, includes a NAND flash memory and a memory controller. The NAND flash memory includes multiple pages, and each page includes multiple sectors. The memory controller receives sector data and a corresponding sector address from the host. The memory controller enables the sector data to be transferred to the NAND flash memory over a first data bus, via a buffer memory, when the sector address is an address for accessing a first sector in a selected page. The memory controller enables the sector data to be transferred to the NAND flash memory over a second data bus, bypassing the buffer memory, when the sector address is an address for accessing a sector other than the first sector in the selected page.

    摘要翻译： 连接到主机的存储卡包括NAND闪存和存储器控制器。 NAND闪存包括多个页面，并且每个页面包括多个扇区。 存储器控制器从主机接收扇区数据和对应的扇区地址。 当扇区地址是用于访问所选择的页面中的第一扇区的地址时，存储器控制器使得扇区数据能够经由缓冲存储器通过第一数据总线传送到NAND快闪存储器。 当扇区地址是用于访问所选页面中的第一扇区之外的扇区的地址时，存储器控制器使扇区数据能够通过第二数据总线传送到NAND闪速存储器，绕过缓冲存储器。

    Flash memory device and method of programming flash memory device
    10.
    发明授权
    Flash memory device and method of programming flash memory device 有权
    闪存设备和闪存设备编程方法

    公开(公告)号：US07746703B2

    公开(公告)日：2010-06-29

    申请号：US12126080

    申请日：2008-05-23

    申请人： Kyong-Ae Kim ,  Jin-Wook Lee ,  Yun-Ho Choi

    发明人： Kyong-Ae Kim ,  Jin-Wook Lee ,  Yun-Ho Choi

    IPC分类号： G11C11/34 ,  G11C16/06

    CPC分类号： G11C16/349

    摘要： A flash memory device and a method of programming the same include a memory cell array, a pass/fail check circuit and a control logic circuit. The memory cell array includes multiple memory cells arranged in rows and columns. The pass/fail check circuit verifies whether data bits selected by a column address during a column scan operation have program data values. The control logic circuit detects fail data bits from the selected data bits and stores the column address in response to the verification result of the pass/fail check circuit. The control logic circuit also compares a number of the fail data bits with a reference value and controls generation of the column address according to the comparison result.

    摘要翻译： 闪速存储器件及其编程方法包括存储单元阵列，通过/失败校验电路和控制逻辑电路。 存储单元阵列包括以行和列排列的多个存储单元。 通过/失败检查电路验证在列扫描操作期间由列地址选择的数据位是否具有程序数据值。 控制逻辑电路根据所选数据位检测故障数据位，并响应于通过/不通过检查电路的验证结果存储列地址。 控制逻辑电路还将多个故障数据位与参考值进行比较，并根据比较结果控制列地址的生成。