公开(公告)号：US6023436A

公开(公告)日：2000-02-08

申请号：US193273

申请日：1998-11-17

Applicant: Yong-joo Han

Inventor： Yong-joo Han

IPC: G11C11/409 ,  G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/02 ,  G11C8/00

CPC classification number: G11C11/4096 ,  G11C11/4091 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/22

Abstract: Integrated circuit memory devices having synchronized bit line selection and I/O line precharge capability include an array of memory cells, a pair of differential bit lines electrically coupled to the array of memory cells, a pair of differential input/output lines and a sense amplifier electrically coupled to the pair of differential input/output lines. An equalization circuit is also provided to equalize the potentials of the pair of differential input/output lines in response to a precharge enable signal. A column select circuit is provided to electrically connect the pair of differential bit lines to the pair of differential input/output lines, in response to a column select enable signal. In addition, a control signal generator is provided to generate the column select enable signal and the precharge enable signal during nonoverlapping time intervals and in-sync with an external clock signal. Using these circuits, the timing margins (e.g., overplus operation margin) associated with the enabling of the precharge signal upon the disabling of the column select signal can be advantageously reduced to enable higher speed operation.

Abstract translation: 具有同步位线选择和I / O线预充电功能的集成电路存储器件包括存储器单元阵列，电耦合到存储器单元阵列的一对差分位线，一对差分输入/输出线和读出放大器 电耦合到该对差分输入/输出线。 还提供均衡电路以响应于预充电使能信号来均衡该对差分输入/输出线的电位。 提供列选择电路以响应于列选择使能信号将该对差分位线电连接到该对差分输入/输出线。 此外，提供控制信号发生器以在非重叠时间间隔期间产生列选择使能信号和预充电使能信号，并与外部时钟信号同步。 使用这些电路，可以有利地减少与禁用列选择信号时的预充电信号的使能相关联的定时裕度（例如，超负荷操作余量），以实现更高速度的操作。

公开(公告)号：US5982688A

公开(公告)日：1999-11-09

申请号：US996918

申请日：1997-12-23

Applicant: Yong-joo Han

Inventor： Yong-joo Han

IPC: G11C11/409 ,  G11C7/12 ,  G11C11/407 ,  G11C11/4094 ,  G11C7/00

CPC classification number: G11C7/12 ,  G11C11/4094

Abstract: A first precharge circuit precharges a bit line to an equalization voltage during precharging operations and is disabled during charge sharing operations floating the bit line. A second precharge circuit precharges a bit line bar to an equalization voltage during precharging and charge sharing operations. Since the bit line is floated during charge sharing operations, and the bit line bar is continually precharged to an equalization voltage level, variation of the bit line bar voltage level due to a charge coupling between the bit line and the bit line bar during charge sharing is prevented. The difference in a level between the bit line and the bit line bar after the charge sharing can be detected by a sense and amplification circuit.

Abstract translation: 第一预充电电路在预充电操作期间将位线预充电到均衡电压，并且在电荷共享操作浮置位线时被禁用。 第二预充电电路在预充电和电荷共享操作期间将位线条预充电到均衡电压。 由于在电荷共享操作期间位线浮置，并且位线条被连续预充电到均衡电压电平，所以在电荷共享期间由位线和位线条之间的电荷耦合引起的位线条电压电平的变化 被阻止 电荷共享后位线和位线条之间的电平差可以由感测和放大电路检测。