公开(公告)号：US08089308B2

公开(公告)日：2012-01-03

申请号：US12421968

申请日：2009-04-10

申请人： Yoshiharu Yoshizawa ,  Yoshito Koyama

发明人： Yoshiharu Yoshizawa ,  Yoshito Koyama

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0805

摘要： In response to an input signal, in a first delay line, a delay amount is added to a phase of the input signal by each delay unit. In a DLL circuit, in response to an external signal that can be externally switched to a signal different in frequency is accepted, in a second delay line, a delay amount is added to the phase of the external signal by each delay unit. The phase of a delay signal delayed by all delay units of the second delay line and the phase of the external signal to which no delay amount added are compared to output a phase difference. A control voltage value that is a value for synchronizing the delay signal to be compared by the phase comparator and is generated from the phase difference output from the phase comparator is input to each of the delay units.

摘要翻译： 响应于输入信号，在第一延迟线中，通过每个延迟单元将延迟量加到输入信号的相位上。 在DLL电路中，响应于能够从外部切换到频率不同的信号的外部信号，在第二延迟线中，通过延迟单元将延迟量加到外部信号的相位上。 延迟信号的延迟相位延迟第二延迟线的所有延迟单元和没有延迟量相加的外部信号的相位，以输出相位差。 作为用于使由相位比较器进行比较的延迟信号和从相位比较器输出的相位差产生的延迟信号同步的值的控制电压值被输入到每个延迟单元。

公开(公告)号：US08049542B2

公开(公告)日：2011-11-01

申请号：US12421968

申请日：2009-04-10

申请人： Yoshiharu Yoshizawa ,  Yoshito Koyama

发明人： Yoshiharu Yoshizawa ,  Yoshito Koyama

IPC分类号： H03L7/06

摘要： In response to an input signal, in a first delay line, a delay amount is added to a phase of the input signal by each delay unit. In a DLL circuit, in response to an external signal that can be externally switched to a signal different in frequency is accepted, in a second delay line, a delay amount is added to the phase of the external signal by each delay unit. The phase of a delay signal delayed by all delay units of the second delay line and the phase of the external signal to which no delay amount added are compared to output a phase difference. A control voltage value that is a value for synchronizing the delay signal to be compared by the phase comparator and is generated from the phase difference output from the phase comparator is input to each of the delay units.

公开(公告)号：US08149033B2

公开(公告)日：2012-04-03

申请号：US12899063

申请日：2010-10-06

申请人： Yoshiharu Yoshizawa ,  Yoshito Koyama

发明人： Yoshiharu Yoshizawa ,  Yoshito Koyama

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/093 ,  H03L7/187

摘要： A DLL circuit includes a delay line that adds, when receiving a reference signal, a delay amount to the phase of the reference signal by using each delay element and outputs a delay signal for each delay element. The DLL circuit includes a phase detector that compares the phase of a delay signal delayed by all the delay elements and the phase of the reference signal to obtain a phase difference by using the delay signal adjusted by a phase adjustment circuit and the reference signal. The DLL circuit includes a delay element control circuit that inputs a value, by which the delay signal to be compared by the phase detector is synchronized with the reference signal to be compared by the phase detector and which is a control voltage value generated from the phase difference output from the phase detector, into the delay elements of the delay line.

摘要翻译： DLL电路包括延迟线，该延迟线通过使用每个延迟元件而在接收参考信号时加上与参考信号的相位相对的延迟量，并输出每个延迟元件的延迟信号。 该DLL电路包括相位检测器，该相位检测器比较所有延迟元件延迟的延迟信号的相位和参考信号的相位，以通过使用由相位调整电路调整的延迟信号和参考信号来获得相位差。 DLL电路包括延迟元件控制电路，其输入值，由相位检测器进行比较的延迟信号与相位检测器进行比较的参考信号同步，并由相位检测器产生的控制电压值 差分输出从相位检测器到延迟线的延迟元件。

公开(公告)号：US20110018601A1

公开(公告)日：2011-01-27

申请号：US12899063

申请日：2010-10-06

申请人： Yoshiharu Yoshizawa ,  Yoshito Koyama

发明人： Yoshiharu Yoshizawa ,  Yoshito Koyama

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/093 ,  H03L7/187

摘要： A DLL circuit includes a delay line that adds, when receiving a reference signal, a delay amount to the phase of the reference signal by using each delay element and outputs a delay signal for each delay element. The DLL circuit includes a phase detector that compares the phase of a delay signal delayed by all the delay elements and the phase of the reference signal to obtain a phase difference by using the delay signal adjusted by a phase adjustment circuit and the reference signal. The DLL circuit includes a delay element control circuit that inputs a value, by which the delay signal to be compared by the phase detector is synchronized with the reference signal to be compared by the phase detector and which is a control voltage value generated from the phase difference output from the phase detector, into the delay elements of the delay line.

摘要翻译： DLL电路包括延迟线，该延迟线通过使用每个延迟元件而在接收参考信号时加上与参考信号的相位相对的延迟量，并输出每个延迟元件的延迟信号。 该DLL电路包括相位检测器，该相位检测器比较所有延迟元件延迟的延迟信号的相位和参考信号的相位，以通过使用由相位调整电路调整的延迟信号和参考信号来获得相位差。 DLL电路包括延迟元件控制电路，其输入值，由相位检测器进行比较的延迟信号与相位检测器进行比较的参考信号同步，并由相位检测器产生的控制电压值 差分输出从相位检测器到延迟线的延迟元件。