公开(公告)号：US20120018805A1

公开(公告)日：2012-01-26

申请号：US13184654

申请日：2011-07-18

申请人： Yoshiki KATO

发明人： Yoshiki KATO

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/0332 ,  H01L21/76224 ,  H01L21/76237 ,  H01L29/1079

摘要： According to embodiments, a semiconductor device includes a semiconductor substrate and an element isolation insulating film which isolates a element formation region in a surface portion of the semiconductor substrate. A depletion-type channel region of a first conductivity type is formed in an inner region which is in the element formation region of the semiconductor substrate and is a predetermined distance or more away from the element isolation insulating film. A gate electrode is formed above the element formation region with a gate insulating film located in between in such a manner as to traverse over the channel region and to overlap with portions of the element isolation insulating film which are located on both sides of the element formation region. Source/drain regions of the first conductivity type are formed in the channel region respectively on both sides of the gate electrode.

摘要翻译： 根据实施例，半导体器件包括半导体衬底和隔离半导体衬底的表面部分中的元件形成区域的元件隔离绝缘膜。 第一导电类型的耗尽型沟道区形成在位于半导体衬底的元件形成区域中的与元件隔离绝缘膜相距预定距离或更远的内部区域中。 栅极电极形成在元件形成区域的上方，栅极绝缘膜位于其间，以便穿过沟道区域并与位于元件形成两侧的元件隔离绝缘膜的部分重叠 地区。 第一导电类型的源/漏区分别形成在栅极两侧的沟道区中。

公开(公告)号：US20120068244A1

公开(公告)日：2012-03-22

申请号：US13236771

申请日：2011-09-20

申请人： Yoshiki KATO

发明人： Yoshiki KATO

IPC分类号： H01L29/788 ,  H01L21/266

CPC分类号： H01L27/11521 ,  H01L29/40114

摘要： According to an embodiment, a semiconductor memory device includes a plurality of multi-level memory cells provided on a major surface of a semiconductor substrate of a first conductivity type. A first semiconductor region of a second conductivity type is selectively provided in the surface of the semiconductor substrate between the multi-level memory cells. A second semiconductor region is provided deeper than the first semiconductor region and includes a first conductivity type impurity. A plurality of binary memory cells are provided on the major surface of the semiconductor substrate, and a third semiconductor region of the second conductivity type is selectively provided in the surface of the semiconductor substrate between the binary memory cells. Amount of the first conductivity type impurity compensating a second conductivity type impurity of the first semiconductor region is larger than that of the third semiconductor region.

摘要翻译： 根据实施例，半导体存储器件包括设置在第一导电类型的半导体衬底的主表面上的多个多电平存储单元。 在多层存储单元之间的半导体衬底的表面中选择性地提供第二导电类型的第一半导体区域。 第二半导体区域被设置为比第一半导体区域更深，并且包括第一导电型杂质。 在半导体衬底的主表面上提供多个二进制存储单元，并且在二进制存储单元之间的半导体衬底的表面中选择性地提供第二导电类型的第三半导体区域。 补偿第一半导体区域的第二导电类型杂质的第一导电类型杂质的量大于第三半导体区域的量。