公开(公告)号：US09269819B2

公开(公告)日：2016-02-23

申请号：US13538877

申请日：2012-06-29

Applicant: Yu Jun Lee

Inventor： Yu Jun Lee

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/10844 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/78642

Abstract: A semiconductor device including a vertical gate and a method for manufacturing the same are disclosed, which prevent a floating body phenomenon, thereby increasing a cell threshold voltage and reducing leakage current, resulting in improved refresh properties of the semiconductor device. The semiconductor device includes a plurality of pillar patterns, including first pillar patterns arranged along a first direction and second pillar patterns arranged along a second direction, formed over a semiconductor substrate; a gate extending in the first direction, arranged along sidewalls of the first pillar patterns, and configured to couple the first pillar patterns; a junction region formed in an upper portion of the pillar patterns; and a conductive line arranged along the sidewalls of the first pillar patterns and provided in a region disposed below the junction region and over the gate.

Abstract translation: 公开了一种包括垂直栅极的半导体器件及其制造方法，其防止浮体现象，从而增加了单元阈值电压并减少漏电流，从而提高了半导体器件的刷新性能。 半导体器件包括：多个柱状图案，包括形成在半导体衬底上的沿着第一方向布置的第一柱状图案和沿着第二方向布置的第二柱状图案; 沿所述第一方向延伸的栅极，沿所述第一柱状图案的侧壁布置，并且被配置为耦合所述第一柱状图案; 形成在柱状图案的上部的接合区域; 以及沿着第一柱状图案的侧壁布置并设置在设置在接合区域下方和栅极之上的区域中的导电线。