公开(公告)号：US20100146373A1

公开(公告)日：2010-06-10

申请号：US12423897

申请日：2009-04-15

申请人： Yuan-Sun CHU ,  Yi-Ren CHEN ,  Chia-Ying HUANG ,  Chi-Fang LI

发明人： Yuan-Sun CHU ,  Yi-Ren CHEN ,  Chia-Ying HUANG ,  Chi-Fang LI

IPC分类号： H03M13/15 ,  G06F11/10

CPC分类号： H04L1/0052 ,  H03M13/15 ,  H04L1/0057

摘要： The present invention discloses a configurable hierarchical comma-free Reed-Solomon decoding circuit and a method thereof. The design is based on an original hierarchical parallel architecture which not only completes a decoding process faster than conventional decoder, but also utilizes less hardware to perform various algorithms with less power consumed. The architecture of the present invention has higher decoding rate than the conventional systolic architecture by a cycle ratio of 22 to 94. Further, the present invention does not require the use of ROM to store 64 sets of codewords and uses logic gates less than one fourth of the logic gates than conventional systolic architecture. As a result, the circuit of the present invention occupies less area than the conventional architecture. The circuit of the present invention is also configurable for different applications, so it can always find an optimal compromise between speed and power consumption for various decoding requirements.

摘要翻译： 本发明公开了一种可配置分层无间断里德 - 索罗门解码电路及其方法。 该设计基于原始的分层并行架构，其不仅比传统解码器更快地完成解码过程，而且还利用较少的硬件来执行具有较少功耗的各种算法。 本发明的架构具有比常规收缩结构更高的解码速率，循环比为22至94.此外，本发明不需要使用ROM来存储64组码字，并且使用小于四分之一的逻辑门 的逻辑门比传统的收缩结构。 结果，本发明的电路占用的面积小于常规架构。 本发明的电路也可以针对不同的应用进行配置，因此它可以总是在各种解码要求之间找到速度和功耗之间的最佳折中。