公开(公告)号：US5058062A

公开(公告)日：1991-10-15

申请号：US431845

申请日：1989-11-06

申请人： Yukio Wada ,  Tadashi Maruyama ,  Toshimasa Nakamura

发明人： Yukio Wada ,  Tadashi Maruyama ,  Toshimasa Nakamura

IPC分类号： G11C17/00 ,  G11C7/06 ,  G11C16/06 ,  G11C16/28

CPC分类号： G11C16/28 ,  G11C7/065

摘要： A nonvolatile memory device has a memory cell having its gate connected to a word line, its source connected to a ground potential and its drain connected to a power supply voltage via a bit line and a dummy cell having its gate connected to the word line, its source connected to the source potential and its drain connected to the power supply voltage via a dummy bit line. The bit line and the dummy bit line are connected to reset and set terminals of a sense amplifier circuit comprising a flip-flop circuit and a latch type of sense amplifier. The conductance of the dummy cell is made smaller than that of the memory cell so that the speed at which the potential on the bit line is lowered depends on the state of injection of electrons into the memory cell as compared with the speed at which the potential on the dummy bit line at a time of reading data. The flip-flop circuit is reset or set in accordance with the speed at which the potential on the bit line is lowered and then the latch type of sense amplifier operates to latch the output of the flip-flop circuit and output it as read data.

公开(公告)号：US5050124A

公开(公告)日：1991-09-17

申请号：US94706

申请日：1987-09-09

申请人： Yukihiro Saeki ,  Toshimasa Nakamura

发明人： Yukihiro Saeki ,  Toshimasa Nakamura

IPC分类号： G11C16/04

CPC分类号： G11C16/0416

摘要： A p-channel MOS transistor is connected in series to a floating gate n-channel MOS transistor forming a memory cell, so that the p-channel MOS transistor functions as the load of the memory cell. The operational characteristic of the p-channel MOS transistor determines the data-writing current of the memory cell. Hence, hardly any change occurs in the data-writing current, even if the operation characteristic of the memory cell changes. A semiconductor memory includes memory cells constituted by floating gate n-channel MOS transistors. The memory further includes a data-reading, column-selecting circuit comprising n-channel MOS transistors, and a data-writing, column-selecting circuit comprising p-channel MOS transistors. By way of the above structure, the data-writing voltage can be prevented from being lowered.

公开(公告)号：US4954991A

公开(公告)日：1990-09-04

申请号：US447391

申请日：1989-12-07

申请人： Yukihiro Saeki ,  Toshimasa Nakamura

发明人： Yukihiro Saeki ,  Toshimasa Nakamura

IPC分类号： G11C16/04

CPC分类号： G11C16/0416

摘要： A p-channel MOS transistor is connected in series to a floating gate n-channel MOS transistor forming a memory cell, so that the p-channel MOS transistor functions as the load of the memory cell. The operational characteristic of the p-channel MOS transistor determines the data-writing current of the memory cell. Hence, hardly any change occurs in the data-writing current, even if the operation characteristic of the memory cell changes. A semiconductor memory includes memory cells constituted by floating gate n-channel MOS transistors. The memory further includes a data-reading, column-selecting circuit comprising n-channel MOS transistors, and a data-writing, column-selecting circuit comprising p-channel MOS transistors. By way of the above structure, the data-writing voltage can be prevented from being lowered.

摘要翻译： p沟道MOS晶体管与形成存储单元的浮置栅极n沟道MOS晶体管串联连接，使得p沟道MOS晶体管起到存储单元的负载的作用。 p沟道MOS晶体管的工作特性决定了存储单元的数据写入电流。 因此，即使存储单元的操作特性发生变化，数据写入电流几乎不发生变化。 半导体存储器包括由浮栅n沟道MOS晶体管构成的存储单元。 存储器还包括包括n沟道MOS晶体管的数据读取列选择电路和包括p沟道MOS晶体管的数据写入列选择电路。 通过上述结构，可以防止数据写入电压降低。