公开(公告)号：US20080159055A1

公开(公告)日：2008-07-03

申请号：US11875171

申请日：2007-10-19

Applicant: Yun-sang LEE ,  Jung-bae LEE

Inventor： Yun-sang LEE ,  Jung-bae LEE

IPC: G11C8/00

CPC classification number: G11C8/08

Abstract: A method and circuit are provided for driving a word line. The word line driving circuit includes first and second power drivers, a switching unit and a word line driver. The first power driver is driven to a boosting voltage level and the second power driver is driven to an internal power voltage level. The switching unit transfers a first output of the first power driver to the word line driver in response to a first switching signal and transfers a second output of the second power driver to the word line driver in response to a second switching signal. The word line driver alternately drives a word line to the first output and the second output transferred from the switching unit in response to a word line driving signal.

Abstract translation: 提供了用于驱动字线的方法和电路。 字线驱动电路包括第一和第二电源驱动器，开关单元和字线驱动器。 第一个功率驱动器被驱动到升压电压电平，第二个功率驱动器被驱动到内部电源电压电平。 切换单元响应于第一切换信号将第一功率驱动器的第一输出传送到字线驱动器，并响应于第二切换信号将第二功率驱动器的第二输出传送到字线驱动器。 字线驱动器响应于字线驱动信号交替地驱动字线到第一输出和从开关单元传送的第二输出。

公开(公告)号：US20080082871A1

公开(公告)日：2008-04-03

申请号：US11863500

申请日：2007-09-28

Applicant: Hoe-ju CHUNG ,  Yun-sang LEE

Inventor： Hoe-ju CHUNG ,  Yun-sang LEE

IPC: G06F11/277 ,  G06F11/25

CPC classification number: G11C29/14 ,  G11C29/12015 ,  G11C2029/3602

Abstract: A semiconductor memory device, having a test mode and a normal mode, includes a frequency multiplier and a test command sequence generator. The frequency multiplier receives a test clock signal in the test mode and generates multiple internal test clock signals, each of which has a frequency equal to a frequency of an operation clock signal in the normal mode. The test clock signal has a frequency lower than the frequency of the operation clock signal. The test command sequence generator generates at least one command signal in response to the internal test clock signals in the test mode. The at least one command signal corresponds to at least one operation timing parameter of the semiconductor memory device that is to be measured. The frequency multiplier may include a Phase Locked Loop (PLL) or a Delay Locked Loop (DLL).

Abstract translation: 具有测试模式和正常模式的半导体存储器件包括倍频器和测试命令序列发生器。 倍频器在测试模式下接收测试时钟信号，并产生多个内部测试时钟信号，每个内部测试时钟信号的频率等于正常模式下的操作时钟信号的频率。 测试时钟信号的频率低于操作时钟信号的频率。 测试命令序列发生器响应于测试模式中的内部测试时钟信号而产生至少一个命令信号。 所述至少一个命令信号对应于待测量的半导体存储器件的至少一个操作定时参数。 倍频器可以包括锁相环（PLL）或延迟锁定环（DLL）。