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公开(公告)号：US08434047B1
公开(公告)日：2013-04-30
申请号：US13013024
申请日：2011-01-25
申请人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
发明人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031 , G06F2217/08
摘要： A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.
摘要翻译： 提供了一种在集成电路（IC）设计中优化时钟选通电路的方法。 确定馈送到多个时钟门的使能输入的多个信号，其中时钟门选通IC设计中的多个顺序元件。 识别在多个信号之间共享的组合逻辑。 时钟门控电路基于共享组合逻辑转换为多级时钟门控电路。
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公开(公告)号：US20080301594A1
公开(公告)日：2008-12-04
申请号：US12128574
申请日：2008-05-28
申请人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
发明人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031 , G06F2217/08
摘要： A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.
摘要翻译： 提供了一种在集成电路（IC）设计中优化时钟选通电路的方法。 确定馈送到多个时钟门的使能输入的多个信号，其中时钟门选通IC设计中的多个顺序元件。 识别在多个信号之间共享的组合逻辑。 时钟门控电路基于共享组合逻辑转换为多级时钟门控电路。
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公开(公告)号：US20080301593A1
公开(公告)日：2008-12-04
申请号：US12128554
申请日：2008-05-28
申请人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
发明人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031 , G06F2217/08
摘要： A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.
摘要翻译： 提供了一种在集成电路（IC）设计的综合网表中导出门控电路的功率优化方法。 合成网表中的块被标识为空闲候选块。 芯片上的子块被聚集成一个集群。 对于集群，基于空闲候选块确定针对功率节省优化的时钟门控结构。 根据时钟门结构，在网表中插入一个或多个不灵活的时钟门。
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公开(公告)号：US07930673B2
公开(公告)日：2011-04-19
申请号：US12128554
申请日：2008-05-28
申请人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
发明人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031 , G06F2217/08
摘要： A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure.
摘要翻译： 提供了一种在集成电路（IC）设计的综合网表中导出门控电路的功率优化方法。 合成网表中的块被标识为空闲候选块。 芯片上的子块被聚集成一个集群。 对于集群，基于空闲候选块确定针对功率节省优化的时钟门控结构。 根据时钟门结构，在网表中插入一个或多个不灵活的时钟门。
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公开(公告)号：US07882461B2
公开(公告)日：2011-02-01
申请号：US12128574
申请日：2008-05-28
申请人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
发明人： Yunjian (William) Jiang , Arvind Srinivasan , Joy Banerjee , Yinghua Li , Partha Das , Samit Chaudhuri
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5031 , G06F2217/08
摘要： A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic.
摘要翻译： 提供了一种在集成电路（IC）设计中优化时钟选通电路的方法。 确定馈送到多个时钟门的使能输入的多个信号，其中时钟门选通IC设计中的多个顺序元件。 识别在多个信号之间共享的组合逻辑。 时钟门控电路基于共享组合逻辑转换为多级时钟门控电路。
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公开(公告)号：US07958476B1
公开(公告)日：2011-06-07
申请号：US12170354
申请日：2008-07-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/78
摘要： A power optimization method of deriving gated circuitry in an integrated circuit (IC) is provided. A design description of the IC is received and analyzed. A state machine is identified based on the analysis. One or more candidate blocks are determined to be capable of being disabled. At least one of the candidate blocks is selected based on one or more states of the state machine. A gating circuit is inserted for gating the selected candidate block(s). In another embodiment of power optimization, one or more state machines are identified and a synthesized netlist is generated. One or more candidate blocks in the synthesized netlist are determined to be capable of being disabled. At least one of the candidate blocks is selected based on one or more states in the state machine, and a gating circuit is inserted for gating the selected candidate block(s).
摘要翻译： 提供了一种在集成电路（IC）中导出门控电路的功率优化方法。 接收并分析IC的设计描述。 基于分析识别状态机。 一个或多个候选块被确定为能够被禁用。 基于状态机的一个或多个状态来选择候选块中的至少一个。 插入门控电路以选通候选块。 在功率优化的另一个实施例中，识别一个或多个状态机，并且生成合成的网表。 合成网表中的一个或多个候选块被确定为能够被禁用。 基于状态机中的一个或多个状态来选择候选块中的至少一个，并且插入门控电路以门控所选择的候选块。
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公开(公告)号：US20100011324A1
公开(公告)日：2010-01-14
申请号：US12479681
申请日：2009-06-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： Techniques are disclosed for improving bit slice placement and wiring. Some embodiments include swapping cells to improve routing. An alternative embodiment includes copying wiring from a first bit slice to a second bit slice. Another embodiment includes copying blocks or cells from a first bit slice to a second bit slice. Further, the wiring from the first bit slice may be copied to the second bit slice.
摘要翻译： 公开了用于改善位片位置和布线的技术。 一些实施例包括交换单元以改善路由。 替代实施例包括将布线从第一位片复制到第二位片。 另一个实施例包括将块或单元从第一位片复制到第二位片。 此外，可以将来自第一位片的布线复制到第二位片。
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公开(公告)号：US08707240B2
公开(公告)日：2014-04-22
申请号：US12479681
申请日：2009-06-05
CPC分类号： G06F17/5072
摘要： Techniques are disclosed for improving bit slice placement and wiring. Some embodiments include swapping cells to improve routing. An alternative embodiment includes copying wiring from a first bit slice to a second bit slice. Another embodiment includes copying blocks or cells from a first bit slice to a second bit slice. Further, the wiring from the first bit slice may be copied to the second bit slice.
摘要翻译： 公开了用于改善位片位置和布线的技术。 一些实施例包括交换单元以改善路由。 替代实施例包括将布线从第一位片复制到第二位片。 另一个实施例包括将块或单元从第一位片复制到第二位片。 此外，可以将来自第一位片的布线复制到第二位片。
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