公开(公告)号：US07473957B2

公开(公告)日：2009-01-06

申请号：US11092794

申请日：2005-03-29

申请人： Yutaka Hayashi ,  Shoji Nakanishi ,  Sumitaka Goto

发明人： Yutaka Hayashi ,  Shoji Nakanishi ,  Sumitaka Goto

IPC分类号： H01L27/108

CPC分类号： H01L29/7885 ,  H01L29/7883

摘要： A floating non-volatile memory has a substrate and source and drain regions disposed in a surface region of the substrate and spaced apart from each other with a channel forming semiconductor region disposed therebetween. A gate insulating film is disposed on the channel forming semiconductor region. A single crystal control region is disposed in the surface region of the substrate and is electrically separated from the channel forming semiconductor region. A control gate insulating film is disposed on the single crystal control region. A floating gate is disposed on the control gate insulating film and is capacitively coupled with the single crystal control region. A chemical-vapor-deposited shield insulating film is formed in a gas atmosphere charge-balanced on the floating gate. A shield conductive film is disposed on the chemical-vapor-deposited shield insulating film and capacitively coupled with the floating gate.

摘要翻译： 浮动非易失性存储器具有衬底和源极和漏极区域，其设置在衬底的表面区域中并且彼此间隔开，并且沟道形成半导体区域位于它们之间。 栅极绝缘膜设置在沟道形成半导体区域上。 单晶控制区域设置在基板的表面区域中，并与沟道形成半导体区域电分离。 控制栅绝缘膜设置在单晶控制区上。 浮置栅极设置在控制栅绝缘膜上并与单晶控制区电容耦合。 在浮动栅极上电荷平衡的气体气氛中形成化学气相沉积的屏蔽绝缘膜。 屏蔽导电膜设置在化学气相沉积的屏蔽绝缘膜上并与浮动栅极电容耦合。

公开(公告)号：US20050221553A1

公开(公告)日：2005-10-06

申请号：US11092794

申请日：2005-03-29

申请人： Yutaka Hayashi ,  Shoji Nakanishi ,  Sumitaka Goto

发明人： Yutaka Hayashi ,  Shoji Nakanishi ,  Sumitaka Goto

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7885 ,  H01L29/7883

摘要： In a non-volatile memory in which a floating gate is provided above a single crystal control region, a potential of wiring, which is arranged above the floating gate, has a capacitive coupling with respect to the floating gate, or even one part in and on an insulating film on the floating gate is included or attached with electric charge, thereby varying the gate threshold voltage of the floating gate non-volatile memory measured from the single crystal control region. In order to solve the above-described problems, the present invention provides following methods. A shield conductive film is provided above a floating gate through a shield insulating film. For the shield insulating film, there is used an insulating film formed by not a deposition method in which a gas atmosphere containing un-balanced charge particles such as excess electrons or excess ions contacts with a wafer surface, such as plasma CVD but a deposition method in which neutral molecules/atoms come flying immediately above the wafer, for example, thermal CVD, radical CVD, photo-assisted CVD, or thermal oxidization.

摘要翻译： 在浮动栅极设置在单晶体控制区域之上的非易失性存储器中，布置在浮置栅极上方的布线电位具有相对于浮动栅极的电容耦合，或甚至一个部分 在浮栅上的绝缘膜上包含或附加电荷，从而改变从单晶控制区测量的浮栅非易失性存储器的栅极阈值电压。 为了解决上述问题，本发明提供以下方法。 屏蔽导电膜通过屏蔽绝缘膜设置在浮栅上。 对于屏蔽绝缘膜，使用通过不是沉积方法形成的绝缘膜，其中包含诸如过电子或过量离子的非平衡电荷颗粒的气体气氛与晶片表面接触，诸如等离子体CVD，但是沉积方法 其中中性分子/原子直接在晶片上方飞行，例如热CVD，自由基CVD，光辅助CVD或热氧化。

公开(公告)号：US20100276778A1

公开(公告)日：2010-11-04

申请号：US12803844

申请日：2010-07-08

申请人： Sumitaka Goto

发明人： Sumitaka Goto

IPC分类号： H01L31/101 ,  H01L31/0352

CPC分类号： H01L31/0248 ,  H01L27/14601 ,  H01L31/103

摘要： A buried oxide is provided in a substrate of a photodiode so as to be opposed to a cathode and is in contact with a lower end of a depletion layer. The buried oxide is polarized owing to charges forming the depletion layer and thus works as a capacitor. A capacitor formed in the depletion layer and the additional capacitor made by the buried oxide are, therefore, connected in series, which reduces a total junction capacitance Cs. Increase in photo-detection voltage Vs results in according to an equation, Vs=Qp/Ct, since an amount of photocharge Qp is constant. The increase in the photo-detection voltage Vs allows an improvement in the SN ratio of the photodiode. Further, easy formation of the buried oxide, for example, by implanting oxygen ions, permits low-cost manufacturing of the photodiode.

摘要翻译： 掩埋氧化物设置在光电二极管的衬底中，以与阴极相对并与耗尽层的下端接触。 掩埋氧化物由于形成耗尽层的电荷而极化，因此用作电容器。 因此，形成在耗尽层中的电容器和由埋入氧化物制成的附加电容器被串联连接，这降低了总结电容Cs。 由于光电荷量Qp恒定，所以根据等式Vs = Qp / Ct导致光检测电压Vs的增加。 光检测电压Vs的增加允许光电二极管的SN比提高。 此外，例如通过注入氧离子容易地形成掩埋氧化物，允许光电二极管的低成本制造。

公开(公告)号：US07768046B2

公开(公告)日：2010-08-03

申请号：US11375295

申请日：2006-03-14

申请人： Sumitaka Goto

发明人： Sumitaka Goto

IPC分类号： H01L31/062 ,  H01L31/113

CPC分类号： H01L31/0248 ,  H01L27/14601 ,  H01L31/103

摘要： An image sensor has a semiconductor substrate of a first conductivity type having a photo-detecting surface and a semiconductor region of a second conductivity type disposed under the photo-detecting surface and forming a junction with the semiconductor substrate. A dielectric body is provided in the semiconductor substrate beneath the junction so that a width of the dielectric body in a direction parallel to the photo-detecting surface does not extend beyond a width of the semiconductor region in the direction parallel to the photo-detecting surface. The dielectric body is polarized due to charges forming a depletion region generated by the semiconductor substrate and the semiconductor region. A width of the dielectric body is approximately equal to a width of an inner surface of the depletion in the direction parallel to the photo-detecting surface of the semiconductor substrate.

摘要翻译： 图像传感器具有第一导电类型的半导体衬底，其具有光检测表面和设置在光检测表面下方的第二导电类型的半导体区域并与半导体衬底形成结。 在半导体衬底的下方设置介电体，使得电介质体在与光检测面平行的方向上的宽度不会延伸超过与光检测面平行的方向的半导体区域的宽度 。 电介质体由于形成由半导体衬底和半导体区域产生的耗尽区域的电荷而极化。 电介质体的宽度大致等于在平行于半导体衬底的光检测表面的方向上的耗尽的内表面的宽度。

公开(公告)号：US20060208333A1

公开(公告)日：2006-09-21

申请号：US11375295

申请日：2006-03-14

申请人： Sumitaka Goto

发明人： Sumitaka Goto

IPC分类号： H01L23/58

CPC分类号： H01L31/0248 ,  H01L27/14601 ,  H01L31/103

摘要： A buried oxide is provided in a substrate of a photodiode so as to be opposed to a cathode and is in contact with a lower end of a depletion layer. The buried oxide is polarized owing to charges forming the depletion layer and thus works as a capacitor. A capacitor formed in the depletion layer and the additional capacitor made by the buried oxide are, therefore, connected in series, which reduces a total junction capacitance Cs. Increase in photo-detection voltage Vs results in according to an equation, Vs=Qp/Ct, since an amount of photocharge Qp is constant. The increase in the photo-detection voltage Vs allows an improvement in the SN ratio of the photodiode. Further, easy formation of the buried oxide, for example, by implanting oxygen ions, permits low-cost manufacturing of the photodiode.

摘要翻译： 掩埋氧化物设置在光电二极管的衬底中，以与阴极相对并与耗尽层的下端接触。 掩埋氧化物由于形成耗尽层的电荷而极化，因此用作电容器。 因此，形成在耗尽层中的电容器和由埋入氧化物制成的附加电容器被串联连接，这降低了总结电容Cs。 由于光电荷量Qp恒定，所以根据等式Vs = Qp / Ct导致光检测电压Vs的增加。 光检测电压Vs的增加允许光电二极管的SN比提高。 此外，例如通过注入氧离子容易地形成掩埋氧化物，允许光电二极管的低成本制造。

公开(公告)号：US06346960B1

公开(公告)日：2002-02-12

申请号：US09404936

申请日：1999-09-23

申请人： Yoshihide Kanakubo ,  Yasuhiro Moya ,  Tatsuya Kitta ,  Kazutoshi Ishii ,  Sumitaka Goto

发明人： Yoshihide Kanakubo ,  Yasuhiro Moya ,  Tatsuya Kitta ,  Kazutoshi Ishii ,  Sumitaka Goto

IPC分类号： B41J2345

CPC分类号： B41J2/355

摘要： A thermal head driving integrated circuit may be used to perform an “n” color or “n” gradation printing operation with a simplified circuit having a reduced size by employing a single delay element connected to a plurality of resistive heating elements. The integrated circuit has a plurality of drive units each for driving a respective one of the heating elements and each having a drive transistor for driving a respective heating element, one or more delay elements, the number of delay elements being less than “n”, for supplying delayed print data to the drive transistor, a print data storing unit for storing the print data of each of the “n” types, and a print data supplying unit for supplying print data stored in the print data storing unit to the “n” delay elements.

摘要翻译： 可以使用热敏头驱动集成电路，通过采用连接到多个电阻加热元件的单个延迟元件，通过具有减小的尺寸的简化电路来执行“n”种颜色或“n”级别打印操作。 集成电路具有多个驱动单元，每个驱动单元用于驱动相应的一个加热元件，并且每个驱动单元具有用于驱动相应加热元件的驱动晶体管，一个或多个延迟元件，延迟元件的数量小于“n” 用于将延迟的打印数据提供给驱动晶体管;打印数据存储单元，用于存储每个“n”类型的打印数据，以及打印数据提供单元，用于将存储在打印数据存储单元中的打印数据提供给“n” “延迟元素