公开(公告)号：US20200059485A1

公开(公告)日：2020-02-20

申请号：US16599051

申请日：2019-10-10

Applicant: Mesut Ergin ,  Ping Yu ,  Declan Doherty ,  Yuwei Zhang

Inventor： Mesut Ergin ,  Ping Yu ,  Declan Doherty ,  Yuwei Zhang

IPC: H04L29/06 ,  H04L12/851 ,  H04L12/931 ,  H04L12/861

Abstract: Methods and apparatus for secure networking protocol optimization via NIC hardware offloading. Under a method, security offload entries are cached in a flow table or a security database offload table on a network interface coupled to a host that implements a host security database mapping flows to Security Association (SA) contexts. Each security offload entry includes information identify a flow and information, such as an offset value, to locate a corresponding entry for the flow in the host security database. Hardware descriptors for received packets that belong to flows with matching security offload entries are generated and marked with the information used to locate the corresponding entries in the host security database. The hardware descriptors are processed by software on the host and the location information is used to de-reference the location of applicable entries in the host security database. In effect, the lookup of matching flows in the host security database is offloaded to the network hardware device.

公开(公告)号：US20070198888A1

公开(公告)日：2007-08-23

申请号：US11380820

申请日：2006-04-28

Applicant: Yuwei Zhang

Inventor： Yuwei Zhang

IPC: H03M13/00

CPC classification number: H03M13/2936 ,  H03M13/253 ,  H03M13/256 ,  H03M13/2948 ,  H03M13/3994

Abstract: A decoding system decodes forward error correction (FEC) encoded data. Factor graph circuitry (such as trellis decoder circuitry) processes the FEC encoded data according to at least one factor graph. Order restoring circuitry (such as convolutional deinterleaver circuitry) is coupled to an output of the factor graph circuitry and restores ordering of symbols in the encoded data. Error detection and correction circuitry is coupled to an output of the order restoring circuitry and processes block-based error correcting codes to detect and correct errors in the FEC encoded data and to provide a hard-decision output to an output of the decoding system. Feedback circuitry (such as convolutional interleaver circuitry and symbol interleaver circuitry) is coupled to process the hard-decision output from the error correction and detection circuitry and to provide the processed hard-decision output to the factor graph circuitry.

Abstract translation: 解码系统解码前向纠错（FEC）编码数据。 因数图电路（例如网格解码器电路）根据至少一个因子图处理FEC编码数据。 订单恢复电路（例如卷积解交织器电路）被耦合到因子图表电路的输出并恢复编码数据中符号的排序。 错误检测和校正电路耦合到订单恢复电路的输出并处理基于块的纠错码，以检测和纠正FEC编码数据中的错误，并向解码系统的输出提供硬判决输出。 耦合反馈电路（例如卷积交织器电路和符号交织器电路）以处理来自纠错和检测电路的硬判决输出，并将经处理的硬决策输出提供给因子图电路。

公开(公告)号：US07680180B2

公开(公告)日：2010-03-16

申请号：US11425602

申请日：2006-06-21

Applicant: Yuwei Zhang ,  Kevin Hwang ,  Jun Lu ,  Shue-Lee Chang

Inventor： Yuwei Zhang ,  Kevin Hwang ,  Jun Lu ,  Shue-Lee Chang

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC classification number: H04L25/03057 ,  H04L25/03267 ,  H04L2025/0349

Abstract: A decision feedback equalizer is configured to equalize an input signal to generate a recovered output signal. Linear feed-forward filter circuitry is configured to provide a linearly filtered output signal based on the input signal. Composite trellis decoder circuitry configured to process a combined signal that is based on a combination of at least the linearly feed-forward filtered output signal and on output of linear or non-linear feedback filter circuitry, in accordance with state metrics generated by processing a composite trellis diagram relative to the combined signal, to provide a trellis-decoded output signal as input to the linear or non-linear feedback filter circuitry. The composite trellis decoder circuitry is further configured to provide a particular phase output of the combined signal, based on the state metrics, as the decoded output signal.

Abstract translation: 判定反馈均衡器被配置为均衡输入信号以产生恢复的输出信号。 线性前馈滤波器电路被配置为基于输入信号提供线性滤波的输出信号。 复合网格解码器电路，被配置为处理基于至少线性前馈滤波的输出信号和线性或非线性反馈滤波器电路的输出的组合的组合信号，根据通过处理复合 网格图相对于组合信号，以提供格状解码的输出信号作为线性或非线性反馈滤波器电路的输入。 复合网格解码器电路还被配置为基于状态度量提供组合信号的特定相位输出作为解码输出信号。

公开(公告)号：US07617435B2

公开(公告)日：2009-11-10

申请号：US11380820

申请日：2006-04-28

Applicant: Yuwei Zhang

Inventor： Yuwei Zhang

IPC: H03M13/00

CPC classification number: H03M13/2936 ,  H03M13/253 ,  H03M13/256 ,  H03M13/2948 ,  H03M13/3994

Abstract: A decoding system decodes forward error correction (FEC) encoded data. Factor graph circuitry (such as trellis decoder circuitry) processes the FEC encoded data according to at least one factor graph. Order restoring circuitry (such as convolutional deinterleaver circuitry) is coupled to an output of the factor graph circuitry and restores ordering of symbols in the encoded data. Error detection and correction circuitry is coupled to an output of the order restoring circuitry and processes block-based error correcting codes to detect and correct errors in the FEC encoded data and to provide a hard-decision output to an output of the decoding system. Feedback circuitry (such as convolutional interleaver circuitry and symbol interleaver circuitry) is coupled to process the hard-decision output from the error correction and detection circuitry and to provide the processed hard-decision output to the factor graph circuitry.

Abstract translation: 解码系统解码前向纠错（FEC）编码数据。 因数图电路（例如网格解码器电路）根据至少一个因子图处理FEC编码数据。 订单恢复电路（例如卷积解交织器电路）被耦合到因子图表电路的输出并恢复编码数据中符号的排序。 错误检测和校正电路耦合到订单恢复电路的输出并处理基于块的纠错码，以检测和纠正FEC编码数据中的错误，并向解码系统的输出提供硬判决输出。 耦合反馈电路（例如卷积交织器电路和符号交织器电路）以处理来自纠错和检测电路的硬判决输出，并将经处理的硬决策输出提供给因子图电路。

公开(公告)号：US20070140329A1

公开(公告)日：2007-06-21

申请号：US11425602

申请日：2006-06-21

Applicant: Yuwei Zhang ,  Kevin Hwang ,  Jun Lu ,  Shue-Lee Chang

Inventor： Yuwei Zhang ,  Kevin Hwang ,  Jun Lu ,  Shue-Lee Chang

IPC: H03H7/30 ,  H04B1/10

CPC classification number: H04L25/03057 ,  H04L25/03267 ,  H04L2025/0349

Abstract: A decision feedback equalizer is configured to equalize an input signal to generate a recovered output signal. Linear feed-forward filter circuitry is configured to provide a linearly filtered output signal based on the input signal. Composite trellis decoder circuitry configured to process a combined signal that is based on a combination of at least the linearly feed-forward filtered output signal and on output of linear or non-linear feedback filter circuitry, in accordance with state metrics generated by processing a composite trellis diagram relative to the combined signal, to provide a trellis-decoded output signal as input to the linear or non-linear feedback filter circuitry. The composite trellis decoder circuitry is further configured to provide a particular phase output of the combined signal, based on the state metrics, as the decoded output signal.

Abstract translation: 判定反馈均衡器被配置为均衡输入信号以产生恢复的输出信号。 线性前馈滤波器电路被配置为基于输入信号提供线性滤波的输出信号。 复合网格解码器电路，被配置为处理基于至少线性前馈滤波的输出信号和线性或非线性反馈滤波器电路的输出的组合的组合信号，根据通过处理复合 网格图相对于组合信号，以提供格状解码的输出信号作为线性或非线性反馈滤波器电路的输入。 复合网格解码器电路还被配置为基于状态度量提供组合信号的特定相位输出作为解码输出信号。