公开(公告)号：US20240020455A1

公开(公告)日：2024-01-18

申请号：US18351464

申请日：2023-07-12

Applicant: ZHEJIANG LAB

Inventor： Zhiquan WAN ,  Shunbin LI ,  Ruyun ZHANG ,  Weihao WANG ,  Qingwen DENG

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F2117/12

Abstract: The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.