公开(公告)号：US20240054597A1

公开(公告)日：2024-02-15

申请号：US18324174

申请日：2023-05-26

Applicant: ZHEJIANG LAB

Inventor： Tang HU ,  Xiao YU ,  Xiangdi LI ,  Songnan REN ,  Li YAN

IPC: G06T1/60

CPC classification number: G06T1/60

Abstract: Disclosed a method and a system for overlapping sliding window segmentation of an image based on an FPGA. According to the method, on-chip BRAMs storage resource cost of FPGA is determined; each on-chip BRAM in FPGA is used to cache the pixel data of each segmented sub-image in parallel; when the pixel data received by the BRAMs reaches a preset threshold or the last pixel of the segmented sub-image is written into the on-chip BRAMs, the data is written from the on-chip BRAMs to an off-chip DDR memory in a burst continuous writing mode; the repeated data generated by segmentation of horizontally overlapping sliding windows are written into the on-chip BRAMs corresponding to the current segmented sub-image and adjacent segmented sub-images thereof respectively in a synchronous and parallel manner.