公开(公告)号：US20230223939A1

公开(公告)日：2023-07-13

申请号：US18183908

申请日：2023-03-14

Applicant: ZHEJIANG LAB

Inventor： Jiani GU ,  Bing CHEN ,  Xiao YU ,  Chengji JIN ,  Genquan HAN

IPC: H03K19/08 ,  H03K19/21

CPC classification number: H03K19/08 ,  H03K19/21 ,  G11C11/223

Abstract: A method, a unit and circuits for implementing Boolean logics based on computing-in-memory transistors. The method is implemented by using the characteristics and the read-write mode of the computing-in-memory transistor; the basic unit consists of a computing-in-memory transistor and a pull resistor; the pull resistor in the basic unit is connected in series with the transistor, and the gate of the transistor is independent; the basic units can implement sixteen Boolean logic operations through different circuit structures and voltage configuration schemes. Compared with the logic circuit structure of the conventional CMOS transistors, the present disclosure can implement more logic operations with fewer transistors, which greatly optimizes circuit density and computing speed caused by data transmission between storage units and process units.

公开(公告)号：US20240078086A1

公开(公告)日：2024-03-07

申请号：US18488991

申请日：2023-10-17

Applicant: ZHEJIANG LAB

Inventor： Jiani GU ,  Xiao YU

IPC: G06F7/503

CPC classification number: G06F7/503

Abstract: The present application discloses a full adder circuit and a multi-bit full adder. In the full adder circuit, an in-memory computing field-effect transistor stores data and performs logic operation on the data in the transistor and the loaded data according to different input signals; and a low-area full adder circuit is realized with very few transistors through the characteristics and the reading and writing modes of the in-memory computing field-effect transistor. The full adder circuit has a simple structure, which is greatly reduces the area and complexity of the full adder circuit, and saves 19 transistors compared with the traditional CMOS full adder circuits.

公开(公告)号：US20240054597A1

公开(公告)日：2024-02-15

申请号：US18324174

申请日：2023-05-26

Applicant: ZHEJIANG LAB

Inventor： Tang HU ,  Xiao YU ,  Xiangdi LI ,  Songnan REN ,  Li YAN

IPC: G06T1/60

CPC classification number: G06T1/60

Abstract: Disclosed a method and a system for overlapping sliding window segmentation of an image based on an FPGA. According to the method, on-chip BRAMs storage resource cost of FPGA is determined; each on-chip BRAM in FPGA is used to cache the pixel data of each segmented sub-image in parallel; when the pixel data received by the BRAMs reaches a preset threshold or the last pixel of the segmented sub-image is written into the on-chip BRAMs, the data is written from the on-chip BRAMs to an off-chip DDR memory in a burst continuous writing mode; the repeated data generated by segmentation of horizontally overlapping sliding windows are written into the on-chip BRAMs corresponding to the current segmented sub-image and adjacent segmented sub-images thereof respectively in a synchronous and parallel manner.