公开(公告)号：US20230388173A1

公开(公告)日：2023-11-30

申请号：US18031575

申请日：2021-07-19

Applicant: ZTE CORPORATION

Inventor： Xingxing CUI ,  Ying DENG ,  Zuofeng ZHANG ,  Yenan BIE ,  Tian TIAN

IPC: H04L27/34 ,  H04B7/0456

CPC classification number: H04L27/3405 ,  H04B7/0456

Abstract: The present disclosure provides a signal processing apparatus and a signal processing method, the signal processing apparatus includes: a preprocessing unit configured to generate a joint matrix according to channel matrixes of subcarriers, and perform a parallel-to-serial conversion on QAM signals of the subcarriers to obtain a serial QAM signal; a judgment unit configured to determine a constraint relationship of a constellation point in each element according to a determining result obtained by determining that whether the constellation point is to be extended in a constellation diagram; a processing unit configured to establish a convex optimization model according to the joint matrix, the serial QAM signal and the determining result, and determine a joint time-domain signal of antenna channels according to the constraint relationship of the constellation point and the convex optimization model; and a conversion unit configured to perform a serial-to-parallel conversion on the joint time-domain signal.

公开(公告)号：US20230379846A1

公开(公告)日：2023-11-23

申请号：US18247933

申请日：2021-07-19

Applicant: ZTE CORPORATION

Inventor： Song CHEN ,  Xuelin LI ,  Yenan BIE

IPC: H04W56/00

CPC classification number: H04W56/001

Abstract: Disclosed are a clock synchronization circuit, a control method, a printed circuit board and a communication device. The clock synchronization circuit includes an external reference signal processing module, a phase detector, a voltage control conversion module, a clock generator, and a first frequency divider.