公开(公告)号：US12160922B2

公开(公告)日：2024-12-03

申请号：US17773695

申请日：2020-10-22

Applicant: ZTE CORPORATION

Inventor： Juntao Wang ,  Gaopeng Du ,  Min Yang ,  Pengzhou Yan ,  Yi Yang

IPC: H04W76/27 ,  H04W36/00 ,  H04W76/15

Abstract: The present application provides an intersecting procedure processing method, an intersecting procedure processing device, an apparatus and a storage medium. The method, applied to a master node, includes: receiving a secondary node procedure message sent by a secondary node; and determining a service processing procedure according to a scenario of a master node service, a scenario of the secondary node procedure and a preset priority of service scenarios, a handover scenario of the secondary node procedure is determined by the secondary node procedure message.

公开(公告)号：US09288154B2

公开(公告)日：2016-03-15

申请号：US14061824

申请日：2013-10-24

Applicant: ZTE CORPORATION

Inventor： Yi Yang ,  Wei Huang ,  Mingshi Sun

IPC: H04L12/863

CPC classification number: H04L47/6225 ,  H04L47/623 ,  H04L47/6295

Abstract: A queue scheduling method and apparatus is disclosed in the embodiments of the present invention, the method comprises: one or more queues are indexed by using a first circulation link list; one or more queues are accessed respectively by using the front pointer of the first circulation link list, and the value acquired from subtracting a value of a unit to be scheduled at the head of the queue from a weight middle value of each queue is treated as the residual weight middle value of the queue; when the weight middle value of one queue in the first circulation link list is less than the unit to be scheduled at the head of the queue, the queue is deleted from the first circulation link list and the weight middle value is updated with the sum of a set weight value and the residual weight middle value of the queue; the queue deleted from the first circulation link list is linked with a second circulation link list. The present invention enables the scheduling to support any number of queues, and supports the expansion of the number of queues under the circumstances that the hardware implementation logic core is not changed.