公开(公告)号：US20050079674A1

公开(公告)日：2005-04-14

申请号：US10683052

申请日：2003-10-09

申请人： Zia Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Weining Li

发明人： Zia Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Weining Li

IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a gate dielectric layer over the semiconductor substrate. The gate dielectric layer is formed in a plurality of thicknesses in a plurality of devices regions over the semiconductor substrate. A second dielectric layer is formed over at least one of the devices regions. A third dielectric layer is formed over at least a portion of the second dielectric layer. Ion traps are then selectively implanted in portions of the second dielectric layer.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底上形成栅介质层。 栅极电介质层在半导体衬底上的多个器件区域中形成多个厚度。 在至少一个器件区域上形成第二介电层。 在第二电介质层的至少一部分上形成第三电介质层。 然后在第二介电层的部分中选择性地注入离子阱。