公开(公告)号：US06499085B2

公开(公告)日：2002-12-24

申请号：US09752846

申请日：2000-12-29

申请人： Zohar Bogin ,  David J. Harriman ,  Zdzislaw A. Wirkus ,  Satish Acharya

发明人： Zohar Bogin ,  David J. Harriman ,  Zdzislaw A. Wirkus ,  Satish Acharya

IPC分类号： G06F1200

CPC分类号： G06F12/0862 ,  G06F12/0835

摘要： A system is described for servicing a full cache line in response to a partial cache line request. The system includes a storage to store at least one cache line, a hit/miss detector, and a data mover. The hit/miss detector receives a partial cache line read request from a requesting agent and dispatches a fetch request to a memory device to fetch a full cache line data that contains data requested in the partial cache line read request from the requesting agent. The data mover loads the storage with the full cache line data returned from the memory device and forwards a portion of the full cache line data requested by the requesting agent. If data specified in a subsequent partial cache line request from the requesting agent is contained within the full cache line data specified in the previously dispatched fetch request, the hit/miss detector will send a command to the data mover to forward another portion of the full cache line data stored in the storage to the requesting agent. In one embodiment, the system also includes a write combining logic to combine two or more consecutive write requests that meet defined conditions into a single write request.