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公开(公告)号:US20060086934A1
公开(公告)日:2006-04-27
申请号:US11293171
申请日:2005-12-05
申请人: Toshiaki Iwamatsu , Yasuo Yamaguchi , Shigenobu Maeda , Shoichi Miyamoto , Akihiko Furukawa , Yasuo Inoue
发明人: Toshiaki Iwamatsu , Yasuo Yamaguchi , Shigenobu Maeda , Shoichi Miyamoto , Akihiko Furukawa , Yasuo Inoue
CPC分类号: H01L21/76297 , H01L21/26586 , H01L21/764 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78606 , H01L29/78612 , H01L29/78633 , H01L29/78654
摘要: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.