公开(公告)号：US08565825B2

公开(公告)日：2013-10-22

申请号：US12476635

申请日：2009-06-02

申请人： Shoichi Miyamoto

发明人： Shoichi Miyamoto

IPC分类号： H04M1/38 ,  H04W4/00 ,  H04W24/00 ,  H04J3/06

CPC分类号： H04B7/0691 ,  H04B7/0413 ,  H04B7/0495 ,  H04B7/0632

摘要： A base station apparatus for performing radio communication with a mobile station in a cell having a plurality of sectors performs a MIMO transmission using an antenna selected from among the antennas provided in each of two sectors when the mobile station moves in the vicinity of the boundary between the sectors. A base station apparatus for performing the radio communication with a mobile station in a cell having no sector structure performs a MIMO transmission using two or more antennas selected from among the antennas when the mobile station moves.

摘要翻译： 用于在具有多个扇区的小区中与移动站进行无线电通信的基站装置在移动台在两个扇区中的每一个中设置的天线中选择的天线之间执行MIMO传输，该天线在 行业。 用于在没有扇区结构的小区中与移动台进行无线通信的基站装置，在移动站移动时，使用从天线中选出的两个以上的天线进行MIMO发送。

公开(公告)号：US07303950B2

公开(公告)日：2007-12-04

申请号：US11034938

申请日：2005-01-14

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/8238

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下面形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US06631142B2

公开(公告)日：2003-10-07

申请号：US09503705

申请日：2000-02-14

申请人： Shoichi Miyamoto ,  Yasuo Tanishima

发明人： Shoichi Miyamoto ,  Yasuo Tanishima

IPC分类号： H04J300

CPC分类号： H04W56/0045

摘要： A delay correction system is used for a wireless telephone system in which a base station apparatus and at least one subscriber apparatus carry out transmitting and receiving operations via respective communication means, in conformance with a time division multiple access (TDMA) system using the base station apparatus as a synchronization reference. The delay correction system includes a measuring instruction input unit for inputting a delay measuring instruction which instructs a delay measurement, a delay measuring unit for measuring a delay quantity between the base station apparatus and the subscriber apparatus, and a first timing adjusting unit, provided in the subscriber apparatus, for receiving transmitting information which is to be sent to the base station apparatus at an allocated time slot, and for adjusting a timing of the transmitting information depending on the delay quantity before sending the transmitting information.

摘要翻译： 延迟校正系统用于无线电话系统，其中基站装置和至少一个用户装置根据使用基站的时分多址（TDMA）系统经由各自的通信装置进行发送和接收操作 装置作为同步参考。 延迟校正系统包括：测量指令输入单元，用于输入指示延迟测量的延迟测量指令;延迟测量单元，用于测量基站装置与用户装置之间的延迟量;以及第一定时调整单元， 用户装置，用于在分配的时隙处接收要发送到基站装置的发送信息，并且用于在发送发送信息之前根据延迟量来调整发送信息的定时。

公开(公告)号：US6144072A

公开(公告)日：2000-11-07

申请号：US231548

申请日：1999-01-15

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

IPC分类号： H01L21/764 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L21/76297 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654 ,  H01L21/26586

摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

公开(公告)号：US5905286A

公开(公告)日：1999-05-18

申请号：US794504

申请日：1997-02-04

申请人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

发明人： Toshiaki Iwamatsu ,  Yasuo Yamaguchi ,  Shigenobu Maeda ,  Shoichi Miyamoto ,  Akihiko Furukawa ,  Yasuo Inoue

IPC分类号： H01L21/764 ,  H01L21/265 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L21/76297 ,  H01L21/764 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78612 ,  H01L29/78633 ,  H01L29/78654 ,  H01L21/26586

摘要： In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

摘要翻译： 在具有SOI结构的半导体器件及其制造方法中，可以防止寄生晶体管的影响，并且与制造过程相关的缺点不会产生。 在该半导体器件中，半导体层的上侧部分是圆形的。 由此，可以防止半导体层的上侧部分的电场集中。 结果，可以防止寄生晶体管的阈值电压的降低，使得寄生晶体管不会对正常晶体管的亚阈值特性产生不利影响。 通过设置U形截面的凹部，当蚀刻用于图案化的栅电极时，可以防止产生蚀刻残留。 因此，不会在制造过程中引起缺点。

公开(公告)号：US4530826A

公开(公告)日：1985-07-23

申请号：US527449

申请日：1983-08-29

申请人： Hiroyuki Ohashi ,  Shoichi Miyamoto ,  Shigeru Kurihara

发明人： Hiroyuki Ohashi ,  Shoichi Miyamoto ,  Shigeru Kurihara

IPC分类号： B01J19/00 ,  F25B27/02 ,  F25B30/04 ,  C07C120/14 ,  C07C121/32 ,  C07C51/16 ,  C01C3/04

CPC分类号： F25B30/04 ,  F25B27/02

摘要： In a process for producing chemical substances comprising steps of cooling, condensing and solvent-absorbing the reaction product gas having a high temperature formed in a reactor, an absorption type refrigerator or an absorption type heat pump is driven by using, as the driving source, a heat source having such a temperature as not to be advantageous for the heat exchange in the process, which heat source has been taken out of the steps of cooling the reaction product gas, condensing it or solvent-absorbing it to obtain a refrigerant or a hot water having a temperature higher than the temperature of the heat source, and the refrigerant or the hot water is used as a cooling source or a heating source in the steps comprised in said process for producing chemical substances.

摘要翻译： 在制造化学物质的方法中，包括在反应器中形成的具有高温的反应产物气体进行冷却，冷凝和溶剂吸收的步骤，通过使用作为驱动源的吸收型冰箱或吸收型热泵， 具有这样的温度的热源，其不利于在该过程中的热交换，该热源已经从冷却反应产物气体，冷凝或溶剂吸收的步骤中取出以获得制冷剂或 温度高于热源的温度的热水，并且制冷剂或热水用作所述生产化学物质的方法中包括的步骤中的冷却源或加热源。

公开(公告)号：US08761275B2

公开(公告)日：2014-06-24

申请号：US12851786

申请日：2010-08-06

申请人： Shoichi Miyamoto

发明人： Shoichi Miyamoto

IPC分类号： H04L27/28 ,  H04L27/00

CPC分类号： H04L5/0041 ,  H04L5/0007 ,  H04L5/0094 ,  H04W72/0453

摘要： A wireless communication technology which realizes high-speed transmission while making effective use of existing frequency bands. A wireless communication apparatus includes a communication unit to perform a wireless communication with a target communication device by simultaneously using a plurality of carrier frequency bands each of which has a specified bandwidth and is discontinuous between each carrier frequency-band interval.

摘要翻译： 一种在有效利用现有频带的同时实现高速传输的无线通信技术。 无线通信装置包括：通信单元，其通过同时使用具有指定带宽的多个载波频带，并且在每个载波频带间隔之间不连续地与目标通信设备进行无线通信。

公开(公告)号：US07741679B2

公开(公告)日：2010-06-22

申请号：US11866693

申请日：2007-10-03

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L23/62

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化膜彼此隔离SOI层中的晶体管形成区域。 在部分氧化膜的下部形成有p型阱区，其将NMOS晶体管彼此隔离，并且在部分氧化膜的下部形成n型阱区，其将PMOS晶体管彼此隔离。 p型阱区域和n型阱区域在部分氧化膜的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域接触。 形成在层间绝缘膜上的互连层通过设置在层间绝缘膜中的体接触电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US20100029321A1

公开(公告)日：2010-02-04

申请号：US12504816

申请日：2009-07-17

申请人： Shoichi Miyamoto

发明人： Shoichi Miyamoto

IPC分类号： H04W52/04 ,  H04B7/005

CPC分类号： H04W52/365 ,  H04W52/282 ,  H04W52/362 ,  H04W52/44

摘要： A mobile station device includes a receiving section configured to receive a control signal used for changing a value of the transmission power of the mobile station device from a base station, and a control section configured to change, if the transmission power value of the mobile station device is more than a certain threshold value when the control signal has been received, the transmission power value by setting an extent to which the transmission power value is to be changed as a certain extent of change, and, if the transmission power value of the radio mobile station device is less than the certain threshold value when the receiving section received, change the transmission power value by making the extent of change of the transmission power value smaller than the certain extent of change.

摘要翻译： 移动站装置包括：接收部，被配置为从基站接收用于改变移动台装置的发送功率的值的控制信号;以及控制部，其被配置为如果所述移动台的发送功率值 当已经接收到控制信号时，设备大于某个阈值，通过设定发送功率值将在一定程度上改变的程度来设置发送功率值，并且如果发送功率值为 当接收部分接收时，无线电移动台装置小于某个阈值，通过使传输功率值的变化程度小于一定的变化范围来改变发射功率值。

公开(公告)号：US20080315313A1

公开(公告)日：2008-12-25

申请号：US11866693

申请日：2007-10-03

申请人： Yasuo YAMAGUCHI ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo YAMAGUCHI ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化膜彼此隔离SOI层中的晶体管形成区域。 在部分氧化膜的下部形成有p型阱区，其将NMOS晶体管彼此隔离，并且在部分氧化膜的下部形成n型阱区，其将PMOS晶体管彼此隔离。 p型阱区域和n型阱区域在部分氧化膜的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域接触。 形成在层间绝缘膜上的互连层通过设置在层间绝缘膜中的体接触电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。