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    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    3.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250014937A1

    公开(公告)日：2025-01-09

    申请号：US18695369

    申请日：2021-09-27

    Applicant: Resonac Corporation

    Inventor： Motoo AOYAMA ,  Kazutaka HONDA ,  Masataka NISHIDA

    IPC: H01L21/683

    Abstract: A method for manufacturing a semiconductor device includes a tape expanding step of stretching an expansion tape while heating to expand an interval between a plurality of semiconductor chips fixed onto the expansion tape at an expansion rate in a range A per one expansion, a transferring step of transferring the plurality of semiconductor chips to an expansion tape, and repeating the tape expanding step and the transferring step. In a stress-strain curve according to a tensile test of the expansion tape, an elongation range B in which an absolute value of a difference between a MD tensile stress and a TD tensile stress is 2.8 MPa or less overlaps with a part of the range A. The tape expanding step includes expanding the interval by using an elongation value selected from an overlapping range between the range A and the range B as the expansion rate per one expansion.

    PREDICTION APPARATUS, TRAINING APPARATUS, PREDICTION METHOD, TRAINING METHOD, PREDICTION PROGRAM, AND TRAINING PROGRAM
    4.
    发明申请
    PREDICTION APPARATUS, TRAINING APPARATUS, PREDICTION METHOD, TRAINING METHOD, PREDICTION PROGRAM, AND TRAINING PROGRAM 有权

    公开(公告)号：US20250014685A1

    公开(公告)日：2025-01-09

    申请号：US18710425

    申请日：2022-11-15

    Applicant: Resonac Corporation

    Inventor： Yu OKANO ,  Takeshi KANESHITA ,  Shimpei TAKEMOTO ,  Katsuki OKUNO ,  Yoshishige OKUNO

    IPC: G16C20/30 ,  G16C20/70

    Abstract: A prediction apparatus includes a trained model trained by using training data in which a material composition of a material to be learned is associated with a phase fraction of the material to be learned at each temperature within a predetermined temperature range, the trained model being configured to predict a phase fraction at an i+1-th temperature by using a phase fraction predicted by the trained model for one or more temperatures up to an i-th temperature within the predetermined temperature range (where i is an integer of 1 or more). The prediction apparatus is configured to input a material composition of a material to be predicted into the trained model, thereby predicting a phase fraction of the material to be predicted at each temperature within the predetermined temperature range.

    Semiconductor device manufacturing method
    7.
    发明授权
    Semiconductor device manufacturing method 有权

    公开(公告)号：US12165882B2

    公开(公告)日：2024-12-10

    申请号：US17612224

    申请日：2020-05-20

    Applicant: Resonac Corporation

    Inventor： Yuta Akasu ,  Emi Miyazawa ,  Takashi Kawamori ,  Shogo Sobue ,  Yasuyuki Oyama

    IPC: H01L21/56 ,  H01L21/02

    Abstract: A method of producing a semiconductor device including: providing a temporary fixing laminate having a supporting substrate; machining a semiconductor member that is temporarily fixed to the supporting substrate; and separating the semiconductor member from the supporting substrate by irradiating the temporary fixing laminate with light from a side of a rear surface of the supporting substrate. A plurality of the irradiation target regions set at the rear surface are sequentially irradiated with light, and each of the irradiation target regions includes a part of the rear surface. The irradiation target regions adjacent to each other partially overlap with each other as viewed from a direction perpendicular to the rear surface, and a region in which the plurality of the irradiation target regions are combined includes the entire rear surface.

    WIRING STRUCTURE, METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR PACKAGE
    9.
    发明申请
    WIRING STRUCTURE, METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20240397635A1

    公开(公告)日：2024-11-28

    申请号：US18791515

    申请日：2024-08-01

    Applicant: RESONAC CORPORATION

    Inventor： Masaya TOBA ,  Kazuyuki MITSUKURA

    IPC: H05K3/38 ,  H01L21/48 ,  H01L23/498 ,  H05K1/09 ,  H05K3/18 ,  H05K3/46

    Abstract: A method for manufacturing a wiring structure includes forming a wiring on an insulating resin layer, which includes forming a modified region including pores in a surface layer of the insulating resin layer by treating a surface of the insulating resin layer with a treatment method including surface modification; forming a seed layer on the surface of the insulating resin layer by sputtering; and forming the wiring on the seed layer by electrolytic copper plating. The method may include, in this order, forming a surface treatment agent layer that covers a surface of the wiring by treating the surface of the wiring with a surface treatment agent for improving adhesion; and forming a modified region including pores in a surface layer of a first layer of the insulating resin layer by treating the surface of the first layer of the insulating resin layer with a treatment method including surface modification.

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