公开(公告)号：US5522086A

公开(公告)日：1996-05-28

申请号：US143363

申请日：1993-10-29

申请人： Mitchell G. Burton ,  Mark J. Wilson

发明人： Mitchell G. Burton ,  Mark J. Wilson

IPC分类号： G06F12/14 ,  G06F13/368

CPC分类号： G06F12/1433

摘要： A mechanism is provided for software configuration of ISA bus cards or other devices connected to a computer processor by a bus that does not provide for sharing of an address by multiple devices. Such a device is configured under software control by selecting multiple addresses commonly used by a read-only device, writing from the computer processor to the configuration logic at one of such addresses a predetermined data word as part of a predetermined security access sequence, writing from the computer processor to the configuration logic at one of the addresses configuration information including a device based address, and the configuration logic, in response to the predetermined security access sequence, storing the configuration information in configuration registers, thereby configuring the device. The addresses used may be addresses used by a game device, such as a joystick. An apparatus for configuring such a device includes multiple configuration registers, circuitry for qualifying access to the configuration registers by verifying compliance with the predetermined security access sequence, the predetermined security access sequence including the central processor writing a predetermined data word to the configuration logic at one of multiple addresses commonly used by a read-only device, and circuitry for, in response to the predetermined security access sequence, storing in the configuration registers configuration information written by the computer processor to one of the multiple addresses, the configuration information including a device base address.

摘要翻译： 提供了一种用于通过不提供多个设备共享地址的总线的ISA总线卡或连接到计算机处理器的其他设备的软件配置的机制。 这样的设备在软件控制下通过选择由只读设备通常使用的多个地址来配置，从计算机处理器将这些地址之一的配置逻辑写入作为预定安全访问序列的一部分的预定数据字，从 计算机处理器响应于预定的安全访问顺序将配置逻辑中的一个地址配置信息（包括基于设备的地址）和配置逻辑存储在配置寄存器中，从而配置该设备。 使用的地址可以是诸如操纵杆的游戏装置使用的地址。 一种用于配置这种设备的装置包括多个配置寄存器，用于通过验证与预定安全访问顺序的一致性来限制对配置寄存器的访问的电路，包括中央处理器的预定安全访问顺序在一个位置上将配置逻辑写入预定数据字 由一个只读设备通常使用的多个地址以及电路，用于响应于预定的安全访问顺序，将由计算机处理器写入的配置寄存器配置信息存储在多个地址之一中，该配置信息包括一个设备 基地址。

公开(公告)号：US5243124A

公开(公告)日：1993-09-07

申请号：US854080

申请日：1992-03-19

申请人： Clifford Kondratiuk ,  Karim Mitha

发明人： Clifford Kondratiuk ,  Karim Mitha

IPC分类号： G10H1/057 ,  G10H7/04 ,  G10H7/12 ,  H03C1/00

CPC分类号： G10H7/04 ,  G10H1/057 ,  G10H7/12 ,  G10H2210/205 ,  G10H2210/211 ,  G10H2210/331 ,  H03C1/00

摘要： A computer having one or more wave tables stored therein is used to synthesize sounds represented by a series of digital samples produced at a sample rate by specifying parameters including a carrier frequency, a modulating frequency and an index of modulation. At each sample time, a modulation value determined during an immediately preceding sample time is scaled to produce a digital control signal. Also at each sample time the modulation value to be used during an immediately succeeding sample time is read from a location of a wave table determined by the modulating frequency, and a carrier value used to produce the digital samples is read from a location of a wave table determined by the carrier frequency and the digital control signal. Modulation effects are therefore delayed by one sample in order to speed execution of the method using the computer. Phase accumulation is performed using a multiplier making it unnecessary to store the sum of all of the previous steps as would be otherwise be required using an additive approach.

摘要翻译： 使用存储有一个或多个波形表的计算机，通过指定包括载波频率，调制频率和调制指数的参数来合成由采样率产生的一系列数字样本所代表的声音。 在每个采样时间，在紧接在前的采样时间之间确定的调制值被缩放以产生数字控制信号。 同样在每个采样时刻，从由调制频率确定的波形表的位置读取在紧随其后的采样时间中要使用的调制值，并且从波的位置读取用于产生数字采样的载波值 表由载波频率和数字控制信号决定。 因此，调制效应被延迟一个样本，以便加速使用计算机的方法的执行。 使用乘法器执行相位累加，使得不需要使用加法方法存储所有先前步骤的总和。