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公开(公告)号：US20220131001A1
公开(公告)日：2022-04-28
申请号：US17572648
申请日：2022-01-11
发明人： HAMZA YILMAZ , JONG OH KIM
IPC分类号： H01L29/78 , H01L29/423 , H01L29/66
摘要： A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
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公开(公告)号：US20210376169A1
公开(公告)日：2021-12-02
申请号：US16936181
申请日：2020-07-22
发明人： Yi-Lung TSAI , Syed Sarwar IMAM , Yao-Wei CHUANG , Ming-Lou TUNG
IPC分类号： H01L29/872 , H01L29/10 , H01L29/06
摘要： A multi-trench schottky diode includes a semiconductor base layer, a back metal layer, an epitaxial layer, an interlayer dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer on the semiconductor base layer includes a termination trench structure, a first trench structure, a second trench structure and a third trench structure. The dielectric layer is on the epitaxial layer in a termination area. The first metal layer stacked on the termination trench structure and the interlayer dielectric layer extends between the second trench structure and the third trench structure. The passivation layer is on the first metal layer and the interlayer dielectric layer. The second metal layer on the first metal layer and the passivation layer extends to the first trench structure. Thus, the electric field is dispersed and the voltage breakdown can be avoided with the trench structures in the termination area.
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公开(公告)号：US20210082792A1
公开(公告)日：2021-03-18
申请号：US16661384
申请日：2019-10-23
发明人： Chien-Chung CHEN , Sen MAO , Peng YEH
IPC分类号： H01L23/495 , H01L21/48 , H01L23/00
摘要： An electric device with terminal notches includes a main body, a plurality of SMT leads and a plurality of plating layers. Each of the SMT leads is extended from the main body and ended up with a lead end surface furnished with a terminal notch, where the terminal notch has a notch peripheral surface. Each of the plating layers covers at least the notch peripheral surface of the corresponding SMT lead. In addition, a method for manufacturing the same electric device with terminal notches is also provided.
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公开(公告)号：US10312183B2
公开(公告)日：2019-06-04
申请号：US15644202
申请日：2017-07-07
发明人： Reyn Qin , Lucy Fan , Meifang Song , Xiaoli Wang
摘要： A die package component with a jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead frame has a die connection surface. The second lead frame is separated to the first lead frame. The second lead frame has a lead frame connection groove which defines a thermal deformation tolerance allowable route. The jumper structure is thermally deformed in a thermal-variable environment. The jumper structure includes a die welding portion and a lead welding portion. The die welding portion is welded to the die. Upon meeting a thermal deformation, the lead welding portion would be movable welded along the thermal deformation tolerance allowable route to the lead frame connection groove.
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公开(公告)号：US10090298B2
公开(公告)日：2018-10-02
申请号：US15447800
申请日：2017-03-02
发明人： Chien-Chung Chen , Sen Mao , Hsin-Liang Lin
IPC分类号： H01L23/495 , H01L27/088 , H01L29/06 , H01L29/417
摘要： An integrated packaging structure is provided. In the package structure, an integrated component body has a first source region, a second source region, a first setting region, and a second setting region, which are separated from each other. A first MOSFET die and a second MOSFET die are located on the first setting region and the second setting region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed from the top surface and spaced apart from each other. A first source connection element is connected to the source electrode pad of the first MOSFET die and the first source region. A second source connection element is connected to the source electrode pad of the second MOSFET die and the second source region. A gate connection element is connected to the gate electrode pad and a gate region of the integrated component body.
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公开(公告)号：US12087831B2
公开(公告)日：2024-09-10
申请号：US18077731
申请日：2022-12-08
发明人： Hamza Yilmaz , Aryadeep Mrinal
IPC分类号： H01L29/40 , H01L21/265 , H01L29/06
CPC分类号： H01L29/404 , H01L21/265 , H01L29/0638
摘要： A high voltage edge termination structure for a power semiconductor device is provided. The high voltage edge termination structure comprises a semiconductor body of a first conductive type, a JTE region of a second conductive type, a heavily doped channel stop region of the first conductive type, and a plurality of field plates. The JTE region is formed in the semiconductor body, wherein the JTE region is adjacent to an active region of the power semiconductor device. The heavily doped channel stop region is formed in the semiconductor body, wherein the heavily doped channel stop region is spaced apart from the JTE region. The plurality of field plates is formed on the JTE region.
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公开(公告)号：US11640993B2
公开(公告)日：2023-05-02
申请号：US17572645
申请日：2022-01-11
发明人： Hamza Yilmaz , Jong Oh Kim
IPC分类号： H01L29/423 , H01L29/78 , H01L29/66
摘要： A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
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公开(公告)号：US11424371B2
公开(公告)日：2022-08-23
申请号：US16936181
申请日：2020-07-22
发明人： Yi-Lung Tsai , Syed Sarwar Imam , Yao-Wei Chuang , Ming-Lou Tung
IPC分类号： H01L29/872 , H01L29/06 , H01L29/10
摘要： A multi-trench schottky diode includes a semiconductor base layer, a back metal layer, an epitaxial layer, an interlayer dielectric layer, a first metal layer, a passivation layer and a second metal layer. The epitaxial layer on the semiconductor base layer includes a termination trench structure, a first trench structure, a second trench structure and a third trench structure. The dielectric layer is on the epitaxial layer in a termination area. The first metal layer stacked on the termination trench structure and the interlayer dielectric layer extends between the second trench structure and the third trench structure. The passivation layer is on the first metal layer and the interlayer dielectric layer. The second metal layer on the first metal layer and the passivation layer extends to the first trench structure. Thus, the electric field is dispersed and the voltage breakdown can be avoided with the trench structures in the termination area.
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公开(公告)号：US20200044078A1
公开(公告)日：2020-02-06
申请号：US16596754
申请日：2019-10-08
发明人： HAMZA YILMAZ , JONG OH KIM
IPC分类号： H01L29/78 , H01L29/66 , H01L29/423
摘要： A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
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公开(公告)号：US10297535B2
公开(公告)日：2019-05-21
申请号：US15948190
申请日：2018-04-09
发明人： Reyn Qin , Lucy Fan , Meifang Song , Xiaoli Wang
摘要： A die package component with a jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead frame has a die connection surface. The second lead frame is separated to the first lead frame. The second lead frame has a lead frame connection groove which defines a thermal deformation tolerance allowable route. The jumper structure is thermally deformed in a thermal-variable environment. The jumper structure includes a die welding portion and a lead welding portion. The die welding portion is welded to the die. Upon meeting a thermal deformation, the lead welding portion would be movable welded along the thermal deformation tolerance allowable route to the lead frame connection groove.
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