公开(公告)号：US08980753B2

公开(公告)日：2015-03-17

申请号：US12886580

申请日：2010-09-21

Applicant: Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chan-Lon Yang

Inventor： Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chan-Lon Yang

IPC: H01L21/311 ,  H01L21/302 ,  H01L21/461 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  B44C1/22 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/823807 ,  H01L21/823814

Abstract: A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.

Abstract translation: 公开了一种用于制造金属栅极晶体管的方法。 该方法包括以下步骤：提供具有第一晶体管区域和第二晶体管区域的衬底; 在第一晶体管区域上形成第一金属氧化物半导体（MOS）晶体管，在第二晶体管区域形成第二MOS晶体管，其中第一MOS晶体管包括第一虚拟栅极，第二MOS晶体管包括第二虚拟栅极; 在所述第二MOS晶体管上形成图案化的硬掩模，其中所述硬掩模包括至少一个金属原子; 以及使用图案化的硬掩模去除第一MOS晶体管的第一伪栅极。

公开(公告)号：US6156603A

公开(公告)日：2000-12-05

申请号：US203020

申请日：1998-12-01

Applicant: Ming-Tsung Tung

Inventor： Ming-Tsung Tung

IPC: H01L21/02 ,  H01L27/06 ,  H01L21/70

CPC classification number: H01L28/60 ,  H01L27/0629

Abstract: The thickness of a capacitor dielectric layer is reduced by a manufacturing method. A first polysilicon layer is deposited on a substrate that has an isolation structure. Subsequently, nitrogen ions are implanted into the first polysilicon layer. The thickness of an oxide layer formed on the first polysilicon layer is determined by dosage of the implanted nitrogen ions. Next, the first polysilicon layer is patterned, so as to form a bottom electrode of the capacitor and expose a portion of the substrate. A thermal oxidation process is then performed to form an oxide layer, which is used as a gate oxide layer on the substrate and is also used as a dielectric layer in capacitor on the bottom electrode. Subsequently, a second polysilicon layer is deposited and patterned as an upper electrode of the capacitor on the capacitor dielectric layer. The thickness of the dielectric layer is affected by implanted nitrogen ions into the first polysilicon layer, so that the dielectric layer is thinner than the gate oxide layer. For this reason, the capacitance is increased, and simultaneously forming the gate oxide layer and the dielectric layer decreases the fabrication cycle time.

Abstract translation: 通过制造方法来减小电容器电介质层的厚度。 第一多晶硅层沉积在具有隔离结构的衬底上。 随后，将氮离子注入第一多晶硅层。 形成在第一多晶硅层上的氧化物层的厚度由注入的氮离子的用量决定。 接下来，对第一多晶硅层进行图案化，以形成电容器的底部电极并暴露基板的一部分。 然后进行热氧化处理以形成氧化物层，其用作衬底上的栅极氧化物层，并且还用作底部电极上的电容器中的电介质层。 随后，沉积第二多晶硅层并将其图案化为电容器介电层上的电容器的上电极。 电介质层的厚度受到将氮离子注入到第一多晶硅层中的影响，使得电介质层比栅极氧化物层薄。 因此，电容增加，同时形成栅极氧化物层和电介质层减少制造周期时间。