公开(公告)号：US08229018B2

公开(公告)日：2012-07-24

申请号：US12885363

申请日：2010-09-17

申请人： James Wight

发明人： James Wight

IPC分类号： H04B7/02

CPC分类号： H04B7/0848 ,  H04B7/0443

摘要： Embodiments of the present invention include systems and methods for optimizing the transmitter and receiver weights of a MIMO system. In one embodiment, the weights are optimized to create and steer beam nulls, such that each transmitted signal is substantially decoupled from all other signals between a MIMO transmitter a MIMO receiver. In another embodiment, the weights are selected such that, the signal strength of each weighted signal transmitted through a communications channel along a respective signal path is substantially equivalent, but for which the weighting vectors are not necessarily orthogonal. In a further embodiment, each transmitted signal is coupled only between its own transmitter and receiver antennas with a gain, or eigenvalue, that is a consequence of the weights, and which is bounded to within a desired range of values while at the same time the weighing vectors are orthogonal. Embodiments employing various decomposition techniques are also provided.

摘要翻译： 本发明的实施例包括用于优化MIMO系统的发射机和接收机权重的系统和方法。 在一个实施例中，权重被优化以创建和引导波束空值，使得每个发射的信号与MIMO发射机之间的MIMO接收机之间的所有其他信号基本上分离。 在另一个实施例中，权重被选择为使得沿着相应信号路径通过通信信道发送的每个加权信号的信号强度基本相等，但是加权矢量不一定是正交的。 在另一个实施例中，每个发送的信号仅在其自己的发射机和接收机天线之间被耦合，其具有作为权重的结果的增益或特征值，并且其被限制在期望的值范围内，同时 称重矢量是正交的。 还提供了使用各种分解技术的实施例。

公开(公告)号：US08107357B2

公开(公告)日：2012-01-31

申请号：US11964510

申请日：2007-12-26

申请人： Maher Amer

发明人： Maher Amer

IPC分类号： H04J11/00 ,  H04L27/00 ,  H04B7/204 ,  G06F17/14

CPC分类号： H04L27/265 ,  G06F17/142 ,  H04L27/263

摘要： We disclose an optimal hardware implementation of the FFT/IFFT operation that minimizes the number of clock cycles required to compute the FFT/IFFT while at the same time minimizing the number of complex multipliers needed. An input module combines a plurality of inputs after applying a multiplication factor to each of the inputs. At least one multiplicand generator generates multiplicands. At least two complex multiplier modules perform complex multiplications with at least one of the complex multiplier modules receiving an output from the input module. A map module receives outputs of the at least two complex multiplier modules, the map module selecting and applying a multiplication factor to each of the outputs received to generate multiple outputs. Finally, an accumulation module receives and performs an accumulation task on each of the multiple outputs of the map module thereby generating a corresponding number of multiple outputs.

摘要翻译： 我们公开了FFT / IFFT操作的最佳硬件实现，其最小化计算FFT / IFFT所需的时钟周期数，同时最小化所需复杂乘法器的数量。 输入模块在将乘法因子应用于每个输入之后组合多个输入。 至少一个被乘数发生器产生被乘数。 至少两个复数乘法器模块执行复数乘法，复数乘法器模块中的至少一个从输入模块接收输出。 地图模块接收至少两个复数乘法器模块的输出，地图模块选择并将乘法因子应用于接收的每个输出以产生多个输出。 最后，积累模块在地图模块的多个输出的每一个上接收并执行累积任务，从而生成相应数量的多个输出。

公开(公告)号：US07280612B2

公开(公告)日：2007-10-09

申请号：US10627881

申请日：2003-07-25

申请人： Aryan Saed

发明人： Aryan Saed

IPC分类号： H04K1/02

CPC分类号： H04L27/368 ,  H04L27/2626

摘要： The present invention provides a digital (computational) branch calibrator which uses a feedback signal sensed from an RF transmit signal path following the combining stage of LINC circuitry of a transmitter to compensate for gain and phase imbalances occurring between branch fragment signals leading to the combiner. The calibrator feeds a quiet (zero) base band signal through the transmit path during the calibration sequence (i.e. a period when data is not transmitted) and adjusts the phase and gain of the phasor fragment signals input thereto by driving the sensed output power to zero. The calibration is performed by alternating phase and gain adjustments with predetermined (programmable) and multiple update parameters stages (speeds). A baseband modulation is preferably used to distinguish false leakage (e.g. due to local oscillator, LO, feed through and DC offset in the base band Tx) from imbalance leakage.

摘要翻译： 本发明提供一种数字（计算）分支校准器，其使用从发射器的LINC电路的组合级之后的RF发射信号路径感测的反馈信号来补偿通向组合器的分支片段信号之间出现的增益和相位不平衡。 校准器在校准序列期间（即，数据未传输的周期）通过发送路径馈送安静的（零）基带信号，并通过将感测的输出功率驱动为零来调整输入到其的相量片段信号的相位和增益 。 通过预定（可编程）和多个更新参数阶段（速度）的交替相位和增益调整来执行校准。 优选地使用基带调制来区分虚泄漏（例如归因于本地振荡器，LO，馈通和基带Tx中的DC偏移）与不平衡泄漏。

公开(公告)号：USRE42612E1

公开(公告)日：2011-08-16

申请号：US11787231

申请日：2007-04-12

申请人： Johan M. Grundingh

发明人： Johan M. Grundingh

IPC分类号： H03F3/217

CPC分类号： H03F3/211 ,  H03F1/0294 ,  H03F1/565 ,  H03F3/217 ,  H03F3/68 ,  H03F2200/391 ,  H03F2200/402

摘要： A switched-mode Class F power amplifier is provided for parallel connection with at least one other like amplifier, within a Chireix architecture, for combining the signals output therefrom. An input component includes at least one active device configured to be alternately switched by a signal input thereto to present an amplified signal corresponding to the input signal and constituting a low output impedance voltage source. A lumped element impedance inverter is provided between the input component and an output resonator component, the impedance inverter being configured for transforming the low output impedance voltage source to instead constitute a high output impedance current source configured for said parallel connection. In accordance with the invention, the negative reactive component values required by the impedance inverter are eliminated and effectively provided by incorporating those values into pre-selected reactive components of the input and output components. Further, a source-drain parasitic capacitance across the active device is eliminated by one or more pre-selected reactive components of the input component, the value(s) of which effectively compensate for the parasitic capacitance.

摘要翻译： 一种开关式F类功率放大器用于与Chireix架构内的至少一个其他类似的放大器并联，用于组合从其输出的信号。 输入部件包括至少一个有源器件，其被配置为通过输入到其中的信号进行交替切换，以呈现对应于输入信号的放大信号并构成低输出阻抗电压源。 集成单元阻抗反相器设置在输入部件和输出谐振器部件之间，阻抗反相器被配置为将低输出阻抗电压源变换为构成用于所述并联连接的高输出阻抗电流源。 根据本发明，通过将这些值并入输入和输出部件的预先选择的无功分量中，可以消除并有效地提供阻抗逆变器所需的负无功分量值。 此外，有源器件两端的源极 - 漏极寄生电容被输入分量的一个或多个预选的电抗分量消除，其中的一个或多个有效元件的值有效补偿寄生电容。

公开(公告)号：US20080268795A1

公开(公告)日：2008-10-30

申请号：US12167217

申请日：2008-07-02

申请人： Aryan Saed

发明人： Aryan Saed

IPC分类号： H04B1/04

CPC分类号： H03F1/3247 ,  H03F2201/3233 ,  H04L25/03343

摘要： Systems and methods related to amplifier systems which use a predistortion subsystem to compensate for expected distortions in the system output signal. A signal processing subsystem receives an input signal and decomposes the input signal into multiple components. Each signal component is received by a predistortion subsystem which applies a predistortion modification to the component. The predistortion modification may be a phase modification, a magnitude modification, or a combination of both and is applied by adjusting the phase of the fragment. The predistorted component is then separately processed by the signal processing subsystem. The processing may take the form of phase modulation and amplification. The phase modulated and amplified components are then recombined to arrive at an amplitude and phase modulated and amplified output signal. The predistortion modification is applied to the components to compensate for distortions introduced in the signal by the signal processing subsystem.

摘要翻译： 与放大器系统相关的系统和方法，其使用预失真子系统来补偿系统输出信号中的预期失真。 信号处理子系统接收输入信号并将输入信号分解为多个分量。 每个信号分量由预失真子系统接收，该预失真子系统对组件应用预失真修改。 预失真修改可以是相位修改，幅度修改或两者的组合，并且通过调整片段的相位来应用。 然后由信号处理子系统单独处理预失真的组件。 该处理可以采取相位调制和放大的形式。 然后将相位调制和放大的分量重新组合以获得幅度和相位调制和放大的输出信号。 预失真修改被应用于组件以补偿信号处理子系统在信号中引入的失真。

公开(公告)号：US07415112B2

公开(公告)日：2008-08-19

申请号：US10629640

申请日：2003-07-29

申请人： Maher Amer

发明人： Maher Amer

IPC分类号： H04L9/20

CPC分类号： H04L25/03872

摘要： Systems, methods and devices for scrambling/descrambling sets of data bits using subsets of a recurring sequence of scrambler bits. A self-synchronous scrambler, regardless of the generating polynomial being implemented, will generate repeating sequences of scrambler bits regardless of the initial stage of the scrambler. To implement a parallel scrambler, given a current state of the scrambler, the next n states of the scrambler are predicted based on the current state of the scrambler. The scrambling operation can then be preformed using the values in the current state—parallel logic operations between preselected bits of the current state will yield the required values to be used in scrambling an incoming parallel data set. Once these required values are generated, a parallel logical operation between the required values and the incoming data set will result in the scrambled output data. The current state of the scrambler is then incremented by n+1 by performing a predetermined set of logical operations between the various bits of the current state such that each bit of the n+1 state is a result of a logical operation between selected and predetermined bits of the current state.

摘要翻译： 用于使用扰频器位的重复序列的子集对数据位进行加扰/解扰组的系统，方法和装置。 无论生成多项式如何，自同步扰频器将产生扰频器比特的重复序列，而不管加扰器的初始阶段如何。 为了实现并行扰频器，给定加扰器的当前状态，基于加扰器的当前状态预测扰频器的下一个n个状态。 然后可以使用当前状态并行逻辑操作中的值来执行加扰操作，当前状态的预选位之间将产生要用于加扰输入并行数据集的所需值。 一旦生成了这些所需的值，则所需值和输入数据组之间的并行逻辑运算将导致加扰的输出数据。 然后，加扰器的当前状态通过执行当前状态的各个比特之间的预定的一组逻辑运算来增加n + 1 + 1，使得n + 1 / SUB>状态是当前状态的选定位和预定位之间的逻辑运算的结果。

公开(公告)号：US07391259B2

公开(公告)日：2008-06-24

申请号：US11490633

申请日：2006-07-21

申请人： Kevin Parker ,  Johan Grundlingh

发明人： Kevin Parker ,  Johan Grundlingh

IPC分类号： H03F1/07 ,  H03F1/33 ,  H03F1/36 ,  H03F3/68

CPC分类号： H03F1/0288 ,  H03F1/3241 ,  H03F3/211

摘要： Embodiments of the present invention comprise methods and devices for amplifying a signal by amplifying a first signal and by then amplifying a second signal only if the first signal exceeds a predetermined threshold. The first and second amplified signals are then combined, and the combination is fed back to a signal source and used to control the values of the first and second signal. The combination is further transmitted to a load. In the preferred embodiment, the first amplified signal is transmitted through an impedance inverter before it is combined with the second amplified signal.

摘要翻译： 本发明的实施例包括通过放大第一信号并且仅当第一信号超过预定阈值时放大第二信号来放大信号的方法和装置。 然后组合第一和第二放大信号，并将该组合反​​馈给信号源，并用于控制第一和第二信号的值。 该组合进一步传输到负载。 在优选实施例中，第一放大信号在与第二放大信号组合之前通过阻抗反相器传输。

公开(公告)号：US20080144753A1

公开(公告)日：2008-06-19

申请号：US12026532

申请日：2008-02-05

申请人： Aryan Saed ,  Phil Guillemette

发明人： Aryan Saed ,  Phil Guillemette

IPC分类号： H04B7/02

CPC分类号： H04B7/0811 ,  H04B7/0814

摘要： The invention relates to the field of wireless communications, more particularly to a method of and device for switching between antennae in communication with a diversity receiver, each of the antennae receiving signals transmitted from a single source. A packet from a transmitter is received by respective antenna communicating with a diversity receiver. The signal strength of the preamble of the packet received in a first antenna is sampled. If the signal strength is of sufficient magnitude to affect reliable reception, the associated antenna is selected for the duration of the packet transmission. If the signal strength is below a predetermined threshold the signal strength of the preamble of the packet received in a second antenna is sampled and compared to the sample associated with the first antenna. If the magnitude of the second sample is greater, the signal associated with the second antenna is selected. To determine the signal strength, the arithmetic average of the signal power over a given period of the preamble is used.

摘要翻译： 本发明涉及无线通信领域，更具体地涉及一种用于在与分集接收机通信的天线之间进行切换的方法和设备，每个天线接收信号从单个源发送。 来自发射机的分组由与分集接收机通信的相应天线接收。 对在第一天线中接收的分组的前导码的信号强度进行采样。 如果信号强度足够大以影响可靠的接收，则在分组传输的持续时间内选择相关联的天线。 如果信号强度低于预定阈值，则对在第二天线中接收的分组的前导码的信号强度进行采样并与与第一天线相关联的采样进行比较。 如果第二样本的幅度较大，则选择与第二天线相关联的信号。 为了确定信号强度，使用在前同步码的给定周期内的信号功率的算术平均值。

公开(公告)号：US20070291863A1

公开(公告)日：2007-12-20

申请号：US11848223

申请日：2007-08-30

申请人： Aryan Saed

发明人： Aryan Saed

IPC分类号： H03K7/06 ,  H04L1/00 ,  H04L5/12

CPC分类号： H04L27/368 ,  H04L27/2626

摘要： The present invention provides a digital (computational) branch calibrator which uses a feedback signal sensed from an RF transmit signal path following the combining stage of LINC circuitry of a transmitter to compensate for gain and phase imbalances occurring between branch fragment signals leading to the combiner. The calibrator feeds a quiet (zero) base band signal through the transmit path during the calibration sequence (i.e. a period when data is not transmitted) and adjusts the phase and gain of the phasor fragment signals input thereto by driving the sensed output power to zero. The calibration is performed by alternating phase and gain adjustments with predetermined (programmable) and multiple update parameters stages (speeds). A baseband modulation is preferably used to distinguish false leakage (e.g. due to local oscillator, LO, feed through and DC offset in the base band Tx) from imbalance leakage.

摘要翻译： 本发明提供一种数字（计算）分支校准器，其使用从发射器的LINC电路的组合级之后的RF发射信号路径感测的反馈信号来补偿通向组合器的分支片段信号之间出现的增益和相位不平衡。 校准器在校准序列期间（即，数据未传输的周期）通过发送路径馈送安静的（零）基带信号，并通过将感测的输出功率驱动为零来调整输入到其的相量片段信号的相位和增益 。 通过预定（可编程）和多个更新参数阶段（速度）的交替相位和增益调整来执行校准。 优选地使用基带调制来区分虚泄漏（例如归因于本地振荡器，LO，馈通和基带Tx中的DC偏移）与不平衡泄漏。

公开(公告)号：US07295066B2

公开(公告)日：2007-11-13

申请号：US11401603

申请日：2006-04-10

申请人： Aryan Saèd

发明人： Aryan Saèd

IPC分类号： H03F1/26

CPC分类号： H03F1/0294 ,  H03F1/3247 ,  H03F1/3282 ,  H03F2201/3233 ,  H04B1/0475

摘要： Systems, methods, and devices relating to the provision of deliberate predistortion to an input signal to compensate for distortions introduced by an amplifier subsystem. An input signal is received by a signal processing system which includes a predistortion subsystem. The input signal is decomposed and the fragments are then predistorted by the predistortion subsystem by applying a deliberate predistortion to the fragments. The predistorted fragments are then separately processed and recombined to arrive at the system output signal. The predistortion subsystem adaptively adjusts based on characteristics of the system output signal. Also, the predistortion subsystem is equipped with a control system that is state based—the state of the predistortion subsystem is dependent upon the prevailing conditions and, when required, the control system switches the state of the predistortion subsystem. A feedback signal, a replica of the system output signal, is used in updating lookup table entries used to determine the predistortion.

摘要翻译： 与向输入信号提供故意预失真相关的系统，方法和设备，以补偿由放大器子系统引入的失真。 输入信号由包括预失真子系统的信号处理系统接收。 输入信号被分解，然后通过对片段应用有意识的预失真，由预失真子系统对片段进行预失真。 然后将预失真的片段分开处理并重新组合以得到系统输出信号。 预失真子系统基于系统输出信号的特性自适应调整。 此外，预失真子系统配备有基于状态的控制系统 - 预失真子系统的状态取决于主要条件，并且在需要时，控制系统切换预失真子系统的状态。 反馈信号（系统输出信号的副本）用于更新用于确定预失真的查找表条目。