公开(公告)号：US20240022453A1

公开(公告)日：2024-01-18

申请号：US18255408

申请日：2021-12-16

Applicant: ISTANBUL MEDIPOL UNIVERSITESI

Inventor： Hüseyin ARSLAN ,  Salah Eddine ZEGRAR

IPC: H04L25/02 ,  H04L27/26

CPC classification number: H04L25/0224 ,  H04L27/2651 ,  H04L27/263

Abstract: Disclosed is a method pilot-aided channel estimation in Orthogonal Frequency Division Multiplexing (OFDM) systems regardless of the frequency selectivity severity of the channel is proposed.

公开(公告)号：US20240291703A1

公开(公告)日：2024-08-29

申请号：US18173600

申请日：2023-02-23

Applicant: Cypress Semiconductor Corporation

Inventor： Harish Chuppala

IPC: H04L27/26 ,  H04L25/02 ,  H04L25/03

CPC classification number: H04L27/2651 ,  H04L25/0202 ,  H04L25/03019

Abstract: One or more devices, systems, and/or methods are provided. In an example of the techniques presented herein, a receiver has a receiver front end configured to receive time domain data in natural order, a fast Fourier transform module configured to generate frequency domain data in digit reversed order based on the time domain data, a demodulator configured to generate first demodulated data in digit reversed order based on the frequency domain data, and a de-interleaver configured to perform a reordering permutation on the first demodulated data to generate second demodulated data in natural order.

公开(公告)号：US20230421425A1

公开(公告)日：2023-12-28

申请号：US17847896

申请日：2022-06-23

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Christopher N. Peters ,  David D. Moser

IPC: H04L27/26 ,  G06F17/14

CPC classification number: H04L27/2651 ,  G06F17/142

Abstract: Techniques are provided for a fast Fourier transform (FFT) sample reorder circuit for a dynamically reconfigurable oversampled channelizer. An FFT sample reorder circuit implementing the techniques according to an embodiment includes a plurality of dual port memory circuits. The circuit also includes a first crossbar circuit configured to route input data samples to write ports of the plurality of dual port memory circuits. The circuit further includes a second crossbar circuit configured to route reordered output data samples from read ports of the plurality of dual port memory circuits to a multi-stage FFT circuit. The circuit further includes a controller circuit configured to control the routing of the input data samples and the routing of the reordered output data samples based on a selection of a stage of the multi-stage FFT circuit.