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    FAST FOURIER TRANSFORM (FFT) BUTTERFLY CIRCUIT FOR A DYNAMICALLY RECONFIGURABLE OVERSAMPLED CHANNELIZER
    1.
    发明公开
    FAST FOURIER TRANSFORM (FFT) BUTTERFLY CIRCUIT FOR A DYNAMICALLY RECONFIGURABLE OVERSAMPLED CHANNELIZER 审中-公开

    公开(公告)号：US20230418899A1

    公开(公告)日：2023-12-28

    申请号：US17847901

    申请日：2022-06-23

    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

    Inventor： Christopher N. Peters ,  David D. Moser

    IPC: G06F17/14

    CPC classification number: G06F17/142

    Abstract: Techniques are provided for a fast Fourier transform (FFT) butterfly circuit. A circuit implementing the techniques according to an embodiment includes a first multiplexer configured to select a first channel or a delayed version of a second channel based on a frame index associated with the first or second channel; a second multiplexer configured to select the channel that was not selected by the first multiplexer; and a butterfly core circuit. The butterfly core circuit configured to receive a delayed version of the selected channel from the first multiplexer as a top butterfly branch; receive the selected channel from the second multiplexer as a bottom butterfly branch; apply FFT twiddle factors to the bottom butterfly branch to generate a scaled bottom butterfly branch; and generate sum and difference channel outputs of the top butterfly branch and the scaled bottom butterfly branch.

    FIREWALL FOR ON-CHIP SIGNALING
    2.
    发明公开
    FIREWALL FOR ON-CHIP SIGNALING 审中-公开

    公开(公告)号：US20230244824A1

    公开(公告)日：2023-08-03

    申请号：US17591699

    申请日：2022-02-03

    Applicant: BAE Systems Information and Electronic Systems Integration Inc.

    Inventor： David D. Moser ,  Daniel L. Stanley ,  Tate J. Keegan ,  Joshua C. Schabel ,  Sheldon L. Grass

    IPC: G06F21/85 ,  G06F12/14

    CPC classification number: G06F21/85 ,  G06F12/1458 ,  G06F2212/1052

    Abstract: An on-chip firewall circuit for providing secure on-chip communication is disclosed. The firewall circuit includes a configurable table of port IDs along with a configurable setting for each port ID to either provide the corresponding port ID with open access to the components of a secure enclave (SE) module or restricted access. If access is restricted, then the command is rerouted to a portion of the secure memory within the SE module, where it can be read only via a secure processing device within the SE module. The secure processing device may require additional verification of the port ID before executing the command stored within the secure memory. In this way, unsecure devices from outside of the SE module can be configured to have no direct access to any of the components within the SE module.

    RADIATION-HARDENED D FLIP-FLOP CIRCUIT
    4.
    发明申请
    RADIATION-HARDENED D FLIP-FLOP CIRCUIT 有权

    公开(公告)号：US20210257999A1

    公开(公告)日：2021-08-19

    申请号：US17307596

    申请日：2021-05-04

    Applicant: BAE Systems Information and Electronic Systems Integration Inc.

    Inventor： Bin Li ,  David Bostedo ,  Landon J. Caley ,  Nicholas J. Chiolino ,  Patrick Fleming ,  David D. Moser

    IPC: H03K3/3562 ,  H03K19/003

    Abstract: A flip-flop and latch circuit is disclosed. The circuit includes a single-input inverter, a dual-input inverter, a single-input tri-state inverter, a dual-input tri-state inverter, and two single-event transient (SET) filters. The single-input tri-state inverter receives an input signal D. The dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the dual-input inverter and the second input receives output signals from the dual-input inverter via the first SET filter. The output of the dual-input tri-state inverter sends output signals to a first input of the dual-input inverter and a second input of the dual-input inverter via the second SET filter. The single-input inverter receives inputs from the dual-input inverter to provide an output signal Q for the circuit

    SECURE SEMICONDUCTOR AND SYSTEM DESIGN
    5.
    发明公开
    SECURE SEMICONDUCTOR AND SYSTEM DESIGN 审中-公开

    公开(公告)号：US20240202375A1

    公开(公告)日：2024-06-20

    申请号：US17907020

    申请日：2022-03-24

    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

    Inventor： David D. Moser ,  Daniel L. Stanley ,  Joshua C. Schabel ,  Tate J. Keegan ,  Sheldon L. Grass

    IPC: G06F21/76 ,  G06F30/347

    CPC classification number: G06F21/76 ,  G06F30/347

    Abstract: A secure system includes a data port, a network on chip (NoC) module, a processor communicatively coupled to the NoC module, a communication interface operatively coupled to the processor and to the data port, an electronic field-programmable gate array (eFPGA) configuration module operatively coupled to the NoC module, and a clock operatively coupled to the NoC module. In a first modality, the communication interface is at least partially disabled. In a second modality, the communication interface is at least partially disabled, boundary scan operations are disabled, a RESET signal is held in a constant state, and/or redacted code is rendered inoperable. In a third modality, the communication interface is at least partially enabled to send and receive commands and data via the data port, the boundary scan operations are enabled, the RESET signal is not held in the constant state, and/or the redacted code is operable.

    Clock phase control
    7.
    发明授权
    Clock phase control 有权

    公开(公告)号：US11108383B1

    公开(公告)日：2021-08-31

    申请号：US17025049

    申请日：2020-09-18

    Applicant: BAE Systems Information and Electronic Systems Integration Inc.

    Inventor： David D. Moser ,  Michael J. Frack ,  Mark R. Shaffer ,  Daniel L. Stanley

    IPC: H03K5/13 ,  H03K5/01 ,  H03K19/21 ,  G06F1/06 ,  G06F1/08 ,  G11C19/28 ,  H03K5/00

    Abstract: A clock phase control circuit includes a clock input gate module, first and second shift register divider modules, and a multiplexer. The clock input gate module is configured to produce, based on an oscillating input clock signal, first and second intermediate clock signals. The first shift register divider module is configured to produce at least one first phase clock signal based on the first intermediate clock signal, where the at least one first phase clock signal has a different frequency than the first intermediate clock signal. The second shift register divider module is configured to produce at least one second phase clock signal based on the second intermediate clock signal, where the at least one second phase clock signal has a different frequency than the second intermediate clock signal. The multiplexer is configured to produce an output clock signal by selecting one of the first or second phase clock signals.

    SEMICONDUCTOR DEVICE WITH REDACTED LOGIC
    9.
    发明申请
    SEMICONDUCTOR DEVICE WITH REDACTED LOGIC 有权

    公开(公告)号：US20250077755A1

    公开(公告)日：2025-03-06

    申请号：US18456648

    申请日：2023-08-28

    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

    Inventor： David D. Moser ,  Daniel L. Stanley ,  Jane O. Gilliam

    IPC: G06F30/343

    Abstract: A semiconductor device includes a data port, a programmable logic block for executing a manufacturer test, and a processor operatively coupled to the data port. The processor is configured to assert, in a first modality, a configuration isolation signal to the data port. The data port is configured to be communicatively isolated from the programmable logic block while the configuration isolation signal is asserted. The processor is configured to de-assert, in a second modality, the configuration isolation signal from the data port. The data port is configured to be communicatively coupled to the programmable logic block while the configuration isolation signal is de-asserted. In some examples, the semiconductor device includes a communication interface communicatively coupled to the programmable logic block, wherein the processor is further configured to cause, in the first modality, data to be loaded into the programmable logic block from a first-in-first-out (FIFO) buffer of the communication interface.

    Triple modular redundancy (TMR) radiation hardened memory system
    10.
    发明授权
    Triple modular redundancy (TMR) radiation hardened memory system 有权

    公开(公告)号：US11861181B1

    公开(公告)日：2024-01-02

    申请号：US17818850

    申请日：2022-08-10

    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

    Inventor： David D. Moser ,  Richard J. Ferguson ,  Daniel L. Stanley

    IPC: G06F11/07 ,  G06F3/06 ,  G06F11/14

    CPC classification number: G06F3/0619 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/0772 ,  G06F11/141

    Abstract: Techniques are provided for a radiation hardened memory system. A memory system implementing the techniques according to an embodiment includes a redundancy comparator configured to detect differences between data stored redundantly in a first memory, a second memory, and a third memory. The redundancy comparator is further configured to identify a memory error based on the detected differences. The memory system also includes an error collection buffer configured to store a memory address associated with the memory error, and a memory scrubber circuit configured to overwrite, at the memory address associated with the memory error, erroneous data with corrected data. The corrected data is based on a majority vote among the three memories. The memory system further includes a priority arbitrator configured to arbitrate between the memory scrubber overwriting and functional memory accesses associated with software execution performed by a processor configured to utilize the memory system.

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