公开(公告)号：US6049490A

公开(公告)日：2000-04-11

申请号：US126302

申请日：1998-07-30

申请人： Atsushi Kawasumi

发明人： Atsushi Kawasumi

IPC分类号： G11C11/41 ,  G11C8/00 ,  G11C13/07

CPC分类号： G11C8/00

摘要： A decoded signal comparison circuit comprises a plurality of decoders, each decoding address signals input in units of at least two bits, the address signals having bits which are input time-sequentially. It also comprises a first register group including a plurality of first registers respectively provided for outputs from the decoders, each first register temporarily storing an output from the corresponding decoder, and a second register group including a plurality of second registers respectively provided for the first registers of the first register group, each second register temporarily storing an output from the corresponding first register. A plurality of bit signal comparison circuits compare a pair of 1-bit signals input thereto. The pair of 1-bit signals consist of the outputs from the first register of the first register group and the second register of the second register group. Each bit signal comparison circuit is activated by one of the pair of 1-bit signals which is output from one of the first and second registers. The number of the bit signal comparison circuits correspond to the number of pairs of first and second registers. A plurality of wired OR circuits are respectively provided for the decoders, for obtaining a logical OR of signals output from the bit signal comparison circuits. A global comparison circuit detects coincidence/non-coincidence of signals output from the wired OR circuits. When the coincidence signal is obtained a Hit signal is outputted.

摘要翻译： 解码信号比较电路包括多个解码器，每个解码地址信号以至少两位为单位输入，地址信号具有按时间顺序输入的位。 它还包括第一寄存器组，其包括分别为来自解码器的输出提供的多个第一寄存器，每个第一寄存器临时存储来自对应解码器的输出;以及第二寄存器组，包括分别为第一寄存器提供的第二寄存器 每个第二寄存器临时存储来自相应的第一寄存器的输出。 多个比特信号比较电路比较输入的一对1比特信号。 一对1位信号由来自第一寄存器组的第一寄存器和第二寄存器组的第二寄存器的输出组成。 每个位信号比较电路由从第一和第二寄存器之一输出的一对1位信号之一激活。 比特信号比较电路的数量对应于第一和第二寄存器的对数。 分别为解码器提供多个有线OR电路，以获得从比特信号比较电路输出的信号的逻辑或。 全局比较电路检测从有线OR电路输出的信号的一致/非重合。 当获得符合信号时，输出命中信号。

公开(公告)号：US06999346B2

公开(公告)日：2006-02-14

申请号：US10774456

申请日：2004-02-10

申请人： In-kyeong Yoo ,  Byong-man Kim

发明人： In-kyeong Yoo ,  Byong-man Kim

IPC分类号： G11C13/07

CPC分类号： B82Y10/00 ,  G11C2216/08 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

摘要： A memory device including a single transistor having functions of RAM and ROM and methods for operating and manufacturing the same are provided. The memory device includes a single transistor formed on a substrate. The transistor may be a memory transistor having a gate with a nonvolatile memory element, or the nonvolatile memory element is provided between the transistor and the substrate.