公开(公告)号：US06704236B2

公开(公告)日：2004-03-09

申请号：US10038021

申请日：2002-01-03

申请人： Myron J. Buer ,  Douglas D. Smith

发明人： Myron J. Buer ,  Douglas D. Smith

IPC分类号： G11C1716

CPC分类号： G11C17/18 ,  G11C17/16 ,  G11C29/38

摘要： A method and circuit for verifying the state of a gated fuse element used with a one-time programmable CMOS memory device. A first expected state is set and a state of a first gate-ox fuse is sensed. The state of the first gate-ox fuse is compared to the first expected state to determine if they are equal, and a first signal is generated. A second expected state is set and a state of a second gate-ox fuse is sensed. The state of the second gate-ox fuse is compared to the second expected state to determine if they are equal, and a second signal is generated. A valid output is generated if both the first and second signals are in a correct state, both signals are high for example.

摘要翻译： 一种用于验证与一次可编程CMOS存储器件一起使用的门控熔丝元件的状态的方法和电路。 设置第一预期状态并且感测到第一栅极 - 氧保险丝的状态。 将第一栅极-nox熔丝的状态与第一预期状态进行比较，以确定它们是否相等，并且产生第一信号。 设定第二预期状态，并且感测到第二栅 - 氧保险丝的状态。 将第二栅极-nox熔丝的状态与第二预期状态进行比较，以确定它们是否相等，并且产生第二信号。 如果第一和第二信号都处于正确状态，则两个信号都为高电平，则产生有效的输出。

公开(公告)号：US06518823B1

公开(公告)日：2003-02-11

申请号：US09645091

申请日：2000-08-24

申请人： Eiji Kawai

发明人： Eiji Kawai

IPC分类号： G11C1716

CPC分类号： G11C7/24 ,  G11C16/22

摘要： An integrated circuit is provided, in which a one-time programmable logic device disables writing to a storage device on the user side once a current is passed therethrough. The integrated circuit has a flash memory operating as a storage device to/from which writing/erasure is possible when a read/write enable port is in a high level. When a power supply is applied to an external power supply input terminal, a fuse having a polysilicon interconnection pattern is blown after a set time period by the output of a step up regulator circuit. After the fuse is blown, the input of a buffer is fixed to a low level through a resistor, so that the read/write enable port of the flash memory as the output of an AND circuit is fixed to a low level and the flash memory becomes a read only memory.

摘要翻译： 提供一种集成电路，其中，一旦电流通过，其中一次性可编程逻辑器件禁用对用户侧的存储设备的写入。 当读/写使能端口处于高电平时，集成电路具有作为存储装置工作的闪存，从而可以进行写入/擦除。 当向外部电源输入端子施加电源时，通过升压调节器电路的输出，在设定的时间段之后熔断具有多晶硅互连图案的熔丝。 熔断器熔断后，缓冲器的输入端通过电阻器固定在低电平，使得与“电路”输出的闪速存储器的读/写使能端口固定为低电平，闪速存储器 成为只读存储器。

公开(公告)号：US06809982B2

公开(公告)日：2004-10-26

申请号：US10437699

申请日：2003-05-14

申请人： Shiro Fujima

发明人： Shiro Fujima

IPC分类号： G11C1716

CPC分类号： G11C29/4401 ,  G11C11/401 ,  G11C29/44 ,  G11C29/785 ,  G11C2029/1208 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is disclosed for remedying defective cells that enables automatic cutting of capacitor fuses as part of the fabrication process. A comparison circuit determines whether defective cells are present in a memory cell array by comparing data that have been read from an I/O bus with data that have been determined in advance to determine whether the data are identical and supplies the determination result as a determination signal. An address buffer circuit, upon receiving a determination signal from the comparison circuit, latches the row address signal and column address signal that are being supplied as output at that time and supplies these latched signals as a capacitor fuse row address signal and a capacitor fuse column address signal for cutting capacitor fuses. Capacitor fuses in a capacitor fuse block are then each cut based on the capacitor fuse row/column address signals that have been latched by the address buffer circuit.

摘要翻译： 公开了一种用于补救有缺陷的电池的方法，该电池能够自动切割电容器保险丝作为制造过程的一部分。 比较电路通过将从I / O总线读取的数据与预先确定的数据进行比较来确定存储单元阵列中是否存在故障单元，以确定数据是否相同，并将确定结果作为确定提供 信号。 地址缓冲电路在从比较电路接收到确定信号时锁存当时作为输出提供的行地址信号和列地址信号，并将这些锁存信号作为电容器熔丝行地址信号和电容器保险丝列 用于切断电容器保险丝的地址信号。 电容器熔断器中的电容器熔丝然后根据地址缓冲电路锁存的电容器熔丝行/列地址信号进行切割。

公开(公告)号：US06339559B1

公开(公告)日：2002-01-15

申请号：US09781883

申请日：2001-02-12

申请人： Claude Louis Bertin ,  John Atkinson Fifield ,  Nicholas Martin van Heel

发明人： Claude Louis Bertin ,  John Atkinson Fifield ,  Nicholas Martin van Heel

IPC分类号： G11C1716

CPC分类号： G11C17/16

摘要： Described is an antifuse array comprising a plurality of antifuse elements and a plurality of cell plates. Each of the antifuse elements comprises a programming transistor and one of the cell plates. The programming transistor and the cell plate of each antifuse element are both activated to program the antifuse element. Each of the cell plates is coupled to a portion of the plurality of antifuse elements and to one of a plurality of decode circuits, and the decode circuits selectively activate its coupled cell plate. With a preferred embodiment, a multitude of interconnect lines are connected to the antifuses and in particular, each interconnect line intersects each of the cell plates and is associated with one antifuse in each group of antifuses. With this preferred embodiment, the array of antifuses are decoded by predecoding one of the cell plates by elevating the cell plate voltage from ground to a program voltage, and decoding one of the interconnect lines to program one of the antifuses. The intersection of the cell plate set to a program voltage and the decoded interconnect line results in programming a unique antifuse.

摘要翻译： 描述了包括多个反熔丝元件和多个单元板的反熔丝阵列。 每个反熔丝元件包括编程晶体管和单元板之一。 每个反熔丝元件的编程晶体管和单元板都被激活以对反熔丝元件进行编程。 每个单元板耦合到多个反熔丝元件的一部分和多个解码电路中的一个，并且解码电路选择性地激活其耦合的单元板。 利用优选实施例，多个互连线连接到反熔丝，并且特别地，每个互连线与每个单元板相交，并且在每组反熔丝组中与一个反熔丝相关联。 利用该优选实施例，通过将单元板电压从地面升高到编程电压，对单元板中的一个进行预解码，并解码其中一条互连线以对其中一个反熔丝进行编译，对反熔丝阵列进行解码。 单元板设置为编程电压和解码的互连线的交点导致编程独特的反熔丝。