公开(公告)号：US5616941A

公开(公告)日：1997-04-01

申请号：US531357

申请日：1995-09-20

申请人： Scott S. Roth ,  Howard C. Kirsch

发明人： Scott S. Roth ,  Howard C. Kirsch

IPC分类号： H01L21/8247 ,  H01L29/423 ,  H01C29/788 ,  H01C27/148

CPC分类号： H01L27/11521 ,  H01L29/42324

摘要： A floating gate (51)is formed to have a cavity (52) that increases the capacitive coupling between the floating gate (51) and a control gate for the memory cell. The memory cell may be used in EPROM, EEPROM, and flash EEPROM arrays and may be programmed and erased by hot carrier injection, Fowler-Nordheim tunneling or the like. The process sequence for forming the cavity (52) of the floating gate (51) has good process margin allowing some lithographic misalignment. In one embodiment, a multi-tiered floating gate may be formed. The multi-tier structure allows the capacitive coupling to further increase without occupying more area.

摘要翻译： 浮动栅极（51）形成为具有增加浮动栅极（51）和存储单元的控制栅极之间的电容耦合的空腔（52）。 存储单元可以用在EPROM，EEPROM和闪存EEPROM阵列中，并且可以通过热载流子注入，Fowler-Nordheim隧道等来编程和擦除。 用于形成浮动栅极（51）的空腔（52）的工艺顺序具有良好的工艺裕度，允许一些光刻未对准。 在一个实施例中，可以形成多层浮动栅极。 多层结构允许电容耦合进一步增加而不占用更多的面积。