公开(公告)号：US10192708B2

公开(公告)日：2019-01-29

申请号：US15356564

申请日：2016-11-19

Applicant: Oregon Physics, LLC

Inventor： Paul P. Tesch ,  Gerald G. Magera

IPC: H01J19/32 ,  H01J19/10 ,  H01J19/38 ,  H01J19/068 ,  H01J21/06 ,  H01J19/82

Abstract: An electron emitter that consists of: a low work function material including Lanthanum hexaboride or Iridium Cerium that acts as an emitter, a cylinder base made of high work function material that has a cone shape where the low work function material is embedded in the high work function material but is exposed at end of the cone and the combined structure is heated and biased to a negative voltage relative to an anode, an anode electrode that has positive bias relative to the emitter, and a wehnelt electrode with an aperture where the cylindrical base protrudes through the wehnelt aperture so the end of the cone containing the emissive area is placed between the wehnelt and the anode.

公开(公告)号：US20170148605A1

公开(公告)日：2017-05-25

申请号：US15356564

申请日：2016-11-19

Applicant: Oregon Physics, LLC

Inventor： Paul P. Tesch ,  Gerald G. Magera

IPC: H01J19/10 ,  H01J21/06 ,  H01J19/068 ,  H01J19/38 ,  H01J19/32

CPC classification number: H01J19/10 ,  H01J19/068 ,  H01J19/32 ,  H01J19/38 ,  H01J19/82 ,  H01J21/06

Abstract: An electron emitter that consists of: a low work function material including Lanthanum hexaboride or Iridium Cerium that acts as an emitter, a cylinder base made of high work function material that has a cone shape where the low work function material is embedded in the high work function material but is exposed at end of the cone and the combined structure is heated and biased to a negative voltage relative to an anode, an anode electrode that has positive bias relative to the emitter, and a wehnelt electrode with an aperture where the cylindrical base protrudes through the wehnelt aperture so the end of the cone containing the emissive area is placed between the wehnelt and the anode.

公开(公告)号：US20190393012A1

公开(公告)日：2019-12-26

申请号：US15991471

申请日：2018-06-22

Applicant: International Business Machines Corporation

Inventor： Injo OK ,  Choonghyun LEE ,  Soon-Cheon SEO ,  Seyoung KIM

IPC: H01J21/10 ,  H01J9/04 ,  H01J19/068

Abstract: A current CMOS technology compatible process to create a planar gate-insulated vacuum channel semiconductor structure. In one example, the structure is created on highly doped silicon. In another example, the structure is created on silicon on insulator (SOI) over a box oxide layer. The planar gate-insulated vacuum channel semiconductor structure is formed over a planar complementary metal-oxide-semiconductor (CMOS) device with a gate stack and a tip-shaped SiGe source/drain region. Shallow trench isolation (STI) is used to form cavities on either side of the gate stack. The cavities are filled with dielectric material. Multiple etching techniques disclosed creates a void in a channel in the tip-shaped SiGe source/drain region under the gate stack. A vacuum is created in the void using physical vapor deposition (PVD) in a region above the tip-shaped SiGe source/drain regions.