专利检索 ipc:"H01L21/76224" 第 1 页

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发明授权
Semiconductor devices including buried gate electrodes and isolation layers and methods of forming semiconductor devices including buried gate electrodes and isolation layers using self aligned double patterning 有权
标题翻译：包括掩埋栅电极和隔离层的半导体器件以及使用自对准双重图案形成半导体器件的方法，包括掩埋栅电极和隔离层

公开(公告)号：US08486818B2

公开(公告)日：2013-07-16

申请号：US12588747

申请日：2009-10-27

申请人： Kye-Hee Yeom

发明人： Kye-Hee Yeom

IPC分类号： H01L21/76224

CPC分类号： H01L29/66621 , H01L21/76224 , H01L27/10814 , H01L27/10823 , H01L27/10891 , H01L27/10894 , H01L27/10897

摘要： A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, and a plurality of buried gate electrodes between a pair of the isolations, wherein each of the buried gate electrodes and the isolations includes a conductive layer and a capping layer.

摘要翻译： 一种半导体器件，包括包括限定半导体衬底的有源区的隔离物的半导体衬底和在一对隔离之间的多个掩埋栅电极，其中每个掩埋栅电极和隔离物包括导电层和覆盖层。