公开(公告)号：US20190198502A1

公开(公告)日：2019-06-27

申请号：US15879929

申请日：2018-01-25

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHING-CHIA HUANG ,  TSENG-FU LU ,  WEI-MING LIAO

IPC分类号： H01L27/108 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L27/10823 ,  H01L27/10891 ,  H01L29/0696 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7827 ,  H01L29/7831

摘要： The present disclosure provides a transistor structure and a semiconductor layout structure. The transistor structure includes an active region, a buried gate structure disposed in the active region, a plurality of first dielectric layers disposed over sidewalls of the buried gate structure, and a source/drain region disposed in the active region at two opposite sides of the buried gate structure. In some embodiments, the buried gate structure includes a first portion and a second portion perpendicular to the first portion. In some embodiments, the buried gate structure is separated from the source/drain region by the first dielectric layers as viewed in a top view.

公开(公告)号：US20190189620A1

公开(公告)日：2019-06-20

申请号：US16177348

申请日：2018-10-31

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Hsu-Yang Wang ,  Ping-Cheng Hsu ,  Shih-Fang Tzou ,  Chin-Lung Lin ,  Yi-Hsiu Lee ,  Koji Taniguchi ,  Harn-Jiunn Wang ,  Tsung-Ying Tsai

IPC分类号： H01L27/108 ,  H01L21/762 ,  H01L21/308

CPC分类号： H01L27/10885 ,  H01L21/3086 ,  H01L21/76224 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891

摘要： A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.

公开(公告)号：US20190080914A1

公开(公告)日：2019-03-14

申请号：US16189368

申请日：2018-11-13

申请人： Lam Research Corporation

发明人： Deqi Wang ,  Anand Chandrashekar ,  Raashina Humayun ,  Michal Danek

IPC分类号： H01L21/285 ,  H01L21/768 ,  C23C16/56 ,  C23C16/02 ,  C23C16/04 ,  C23C16/06 ,  C23C16/505 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/108

CPC分类号： H01L21/28556 ,  C23C16/0245 ,  C23C16/04 ,  C23C16/045 ,  C23C16/06 ,  C23C16/505 ,  C23C16/56 ,  H01L21/28562 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76898 ,  H01L27/10891 ,  H01L27/11556 ,  H01L27/11582

摘要： Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. The methods include performing multi-stage inhibition treatments including intervals between stages. One or more of plasma source power, substrate bias power, or treatment gas flow may be reduced or turned off during an interval. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.

公开(公告)号：US20190006369A1

公开(公告)日：2019-01-03

申请号：US15979476

申请日：2018-05-15

申请人： Winbond Electronics Corp.

发明人： Wei-Che Chang ,  Yoshinori Tanaka

IPC分类号： H01L27/108 ,  H01L29/06 ,  H01L21/762

CPC分类号： H01L27/10891 ,  H01L21/76224 ,  H01L27/10823 ,  H01L27/10876 ,  H01L29/0649

摘要： A semiconductor structure includes a substrate, and first isolation structures, at least one buried word line and at least one second isolation structure which are disposed in the substrate. The buried word line intersects the first isolation structures. The second isolation structure intersects the first isolation structures. A material of at least a portion of the second isolation structure is different from a material of the first isolation structures.

公开(公告)号：US20180358362A1

公开(公告)日：2018-12-13

申请号：US15867079

申请日：2018-01-10

申请人： Winbond Electronics Corp.

发明人： Ying-Chu YEN ,  Wei-Che CHANG ,  Yoshinori TANAKA

IPC分类号： H01L27/108 ,  H01L29/06 ,  H01L21/762

CPC分类号： H01L27/10891 ,  H01L21/76224 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/0649

摘要： A memory device includes a semiconductor substrate having at least one active area that is defined by a device isolation structure. The memory device further includes two neighboring buried word lines disposed in the semiconductor substrate of the active area. The memory device further includes a trench isolation structure disposed in the semiconductor substrate between the buried word lines.

公开(公告)号：US20180286742A1

公开(公告)日：2018-10-04

申请号：US15865267

申请日：2018-01-09

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Yukihiro Nagai

IPC分类号： H01L21/761 ,  H01L27/108 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234

CPC分类号： H01L21/761 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/0649 ,  H01L2924/14

摘要： A semiconductor structure includes a substrate with a first conductivity type and a first doping concentration, an active area with its longitudinal axis extending along a first direction, a trench isolation structure contiguous with an end surface of the active area, a passing gate in the trench isolation structure and extending along a second direction that is not parallel with the first direction, and a localized doping region with a second conductivity type and a second doping concentration that is located on the end surface.

公开(公告)号：US10056288B1

公开(公告)日：2018-08-21

申请号：US15672272

申请日：2017-08-08

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Tsuo-Wen Lu ,  Chin-Wei Wu ,  Tien-Chen Chan ,  Ger-Pin Lin ,  Shu-Yen Chan

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L27/108 ,  H01L29/423 ,  H01L21/764 ,  H01L21/02

CPC分类号： H01L21/76237 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/764 ,  H01L21/823481 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236

摘要： A semiconductor device includes a semiconductor substrate having a gate trench penetrating through an active area and a trench isolation region surrounding the active area. The gate trench exposes a sidewall of the active area and a sidewall of the trench isolation region. The sidewall of the trench isolation region includes a void. A first gate dielectric layer conformally covers the sidewall of the active area and the sidewall of the trench isolation region. The void in the sidewall of the trench isolation region is filled with the first gate dielectric layer. A second gate dielectric layer is grown on the sidewall of the active area. A gate is embedded in the gate trench.

公开(公告)号：US20180182765A1

公开(公告)日：2018-06-28

申请号：US15391604

申请日：2016-12-27

申请人： Micron Technology, Inc.

发明人： Werner Juengling

IPC分类号： H01L27/108

CPC分类号： H01L27/10879 ,  H01L27/10814 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10891

摘要： Some embodiments include a method of forming a memory array. A wordline is formed to extend along a first direction, and along a rail of semiconductor material. After the wordline is formed, the rail is patterned into fins. Each fin has a first pedestal, a second pedestal, and a trough between the first and second pedestals. Charge-storage devices are formed to be electrically coupled with the first pedestals. Digit lines are formed to be electrically coupled with the second pedestals. Some embodiments include apparatuses containing finFETs.

公开(公告)号：US20180151570A1

公开(公告)日：2018-05-31

申请号：US15881391

申请日：2018-01-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chin-Shan WANG ,  Shun-Yi LEE

IPC分类号： H01L27/108

CPC分类号： H01L27/10832 ,  H01L21/823878 ,  H01L27/10826 ,  H01L27/1085 ,  H01L27/1087 ,  H01L27/10879 ,  H01L27/10891

摘要： A semiconductor device includes a substrate. The semiconductor device further includes a first transistor on the substrate, wherein the first transistor includes a first source/drain electrode. The semiconductor device further includes a second transistor on the substrate, wherein the second transistor includes a second source/drain electrode. The semiconductor device further includes an insulating layer extending into the substrate, wherein the insulating layer directly contacts the first source/drain electrode and the second source/drain electrode.

公开(公告)号：US09893070B2

公开(公告)日：2018-02-13

申请号：US15178903

申请日：2016-06-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chin-Shan Wang ,  Shun-Yi Lee

IPC分类号： H01L23/48 ,  H01L27/108

CPC分类号： H01L27/10832 ,  H01L27/10826 ,  H01L27/1085 ,  H01L27/1087 ,  H01L27/10879 ,  H01L27/10891

摘要： A method of fabricating a semiconductor device. The method includes forming a dummy structure over a substrate, forming conductive features on opposite sides of the dummy gate structure, removing the dummy structure and a portion of the substrate beneath the dummy gate structure to form a trench, and filling the trench with a dielectric material.