公开(公告)号：US06445043B1

公开(公告)日：2002-09-03

申请号：US08347527

申请日：1994-11-30

申请人： Sailesh Chittipeddi

发明人： Sailesh Chittipeddi

IPC分类号： H01L2516

CPC分类号： H01L21/76224

摘要： A process for forming isolated active device regions on a silicon substrate comprises the steps of forming at least one trench in a silicon substrate to define at least two active device regions on the substrate to be isolated from each other, depositing an electrically insulative material on the substrate to fill the trench with the material, planarizing the surface of the substrate, performing a masking and etching operation to expose at least one active device region on the substrate, selectively growing a first epitaxial layer of silicon on the exposed active device region, masking the substrate to leave exposed at least one other active device region on the substrate, selectively growing a second epitaxial layer of silicon on the other exposed active device region, the first epitaxial layer and second epitaxial layer being doped with dopant atoms to the same or different dopant concentration to provide, at least two isolated active device regions on the silicon substrate. The process of the invention enables the fabrication of performance optimized MOS-type and bipolar devices simultaneously and independently of each other on a single clip or wafer.

摘要翻译： 在硅衬底上形成隔离的有源器件区域的工艺包括以下步骤：在硅衬底中形成至少一个沟槽，以在衬底上限定至少两个有源器件区域以彼此隔离;将电绝缘材料沉积在 衬底以用材料填充沟槽，平坦化衬底的表面，执行掩模和蚀刻操作以暴露衬底上的至少一个有源器件区域，在暴露的有源器件区域上选择性地生长硅的第一外延层，掩蔽 衬底以在衬底上留下暴露的至少一个其它有源器件区域，在另一暴露的有源器件区域上选择性地生长硅的第二外延层，第一外延层和第二外延层掺杂有相同或不同的掺杂剂原子 掺杂剂浓度以在硅衬底上提供至少两个隔离的有源器件区域。 本发明的方法使得能够在单个夹子或晶片上同时且彼此独立地制造性能优化的MOS型和双极器件。

公开(公告)号：US06787881B2

公开(公告)日：2004-09-07

申请号：US10038753

申请日：2002-01-04

申请人： Romeo Letor ,  Antonino Torres ,  Leonardo Fragapane

发明人： Romeo Letor ,  Antonino Torres ,  Leonardo Fragapane

IPC分类号： H01L2516

CPC分类号： H01L27/0248

摘要： An integrated power device having a power transistor made up of a first diode and a second diode that are connected together in series between a collector region and emitter-contact region of the power transistor to define a common intermediate node, a control circuit including a high-voltage region bonded on the emitter-contact region (14) by means of an adhesive layer, and biasing circuit connected between the common intermediate node and the high-voltage region. The biasing circuit including a contact pad electrically connected to the common intermediate node, an electrical connection region that is in electrical contact with the high-voltage region (30), and a wire having a first end soldered on the contact pad and a second end soldered on said electrical connection region.

摘要翻译： 一种具有由第一二极管和第二二极管组成的功率晶体管的集成功率器件，其串联连接在功率晶体管的集电极区域和发射极 - 接触区域之间，以限定公共中间节点，控制电路包括高 - 电压区域，通过粘合剂层结合在发射极 - 接触区域（14）上，以及偏置电路，连接在公共中间节点和高压区域之间。 所述偏置电路包括电连接到所述公共中间节点的接触焊盘，与所述高压区域（30）电接触的电连接区域，以及具有焊接在所述接触焊盘上的第一端的导线，以及第二端 焊接在所述电连接区域上。