公开(公告)号：US5838050A

公开(公告)日：1998-11-17

申请号：US932010

申请日：1997-09-17

申请人： Ming-Dou Ker ,  Chung-Yu Wu ,  Chien-Chang Huang ,  Chau-Neng Wu ,  Ta-Lee Yu

发明人： Ming-Dou Ker ,  Chung-Yu Wu ,  Chien-Chang Huang ,  Chau-Neng Wu ,  Ta-Lee Yu

IPC分类号： H01L27/02 ,  H01L27/092 ,  H01L27/72

CPC分类号： H01L27/0251 ,  H01L27/092

摘要： A CMOS device containing a plurality of hexagon cells over a semiconductor substrate is disclosed. Each hexagon cell includes a hexagonal ring gate, a drain diffusion region and a source diffusion region. The hexagonal ring gate is made of conducting materials and a dielectric layer over the substrate, therefore defining a channel region in the substrate between the gate and the substrate. The entire drain diffusion region in the substrate is enclosed by the hexagonal ring gate. The source diffusion region surrounds the hexagonal ring gate in the substrate. Each hexagon cell further provides a drain contact in the center of the drain diffusion region. A plurality of source contacts are arranged around the ring gate over the substrate. The hexagon cells of a unique hexagon device are surrounded by a first guard ring and a second guard ring. The hexagon device can be used as a CMOS output buffer or input ESD protection circuit to reduce the layout area of an integrated circuit.

摘要翻译： 公开了一种在半导体衬底上包含多个六边形单元的CMOS器件。 每个六边形单元包括六边形环形栅极，漏极扩散区域和源极扩散区域。 六角环形栅极由导电材料和介质层构成，因此在栅极和衬底之间在衬底中限定沟道区。 衬底中的整个漏极扩散区域被六边形环形栅极包围。 源极扩散区域围绕衬底中的六角形环形栅极。 每个六边形单元还在漏极扩散区域的中心处提供漏极接触。 在环形栅极周围多个源极触点布置在衬底上。 独特的六边形装置的六边形单元被第一保护环和第二保护环包围。 六边形器件可用作CMOS输出缓冲器或输入ESD保护电路，以减少集成电路的布局面积。

公开(公告)号：US06989557B2

公开(公告)日：2006-01-24

申请号：US10709569

申请日：2004-05-14

申请人： Anchor Chen

发明人： Anchor Chen

IPC分类号： H01L27/72

CPC分类号： H01L29/66242 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/7378

摘要： A bipolar junction transistor (BJT) includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a heavily doped polysilicon layer formed on a sidewall of the opening to define a self-aligned base region in the opening, an intrinsic base doped region formed within the substrate and in a bottom of the opening by implanting through the self-aligned base region, a spacer formed on the heavily doped polysilicon layer to define a self-aligned emitter region in the opening, and an emitter conductivity layer being filled with the self-aligned emitter region and a PN junction being formed between the emitter conductivity layer and the intrinsic base doped region.