公开(公告)号：US5900658A

公开(公告)日：1999-05-04

申请号：US950233

申请日：1997-10-14

申请人： Jin-Yuan Lee ,  Chue-San Yoo ,  Mong-Song Liang

发明人： Jin-Yuan Lee ,  Chue-San Yoo ,  Mong-Song Liang

IPC分类号： H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L7/01

CPC分类号： H01L27/10844 ,  H01L21/823425 ,  H01L27/088

摘要： A semiconductor fabrication process has been developed in which both DRAM and logic device structures are integrated on a single silicon chip. The process features combining process steps for both device types, while using only a single level of polysilicon for both a high capacity DRAM cell, as well as for a CMOS logic cell. The high capacity DRAM cell is composed of an overlying polysilicon storage gate structure, a thin dielectric layer, and an underlying doped semiconductor regions.

摘要翻译： 已经开发了半导体制造工艺，其中DRAM和逻辑器件结构都集成在单个硅芯片上。 该过程的特征是组合了两种器件类型的工艺步骤，同时对于高容量DRAM单元以及CMOS逻辑单元仅使用单层多晶硅。 高容量DRAM单元由上覆多晶硅存储栅结构，薄介电层和下掺杂半导体区构成。